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Mont-Blanc 2020 SIGNED

Mont-Blanc 2020, European scalable, modular and power efficient HPC processor

Total Cost €

EC-Contrib. €

Partnership

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Outcomes and
results

Mont-Blanc 2020 project word cloud

Explore the words cloud of the Mont-Blanc 2020 project. It provides you a very rough idea of what is the project "Mont-Blanc 2020" about.

arm extension performance market outperform explore generation time offers ecosystem life modular innovative reliability lays power energy ambitions mandatory foundation competition hpc server co instruction noc packaging watt 2020 introduce scalable exascale markets innovations 2022 mb2020 soc components processor chip modules relevance 5d sustainability economic leverage retarget vector technologies delivering scheduled isa mont versatility latency prototype security successful serve gflops integration choices blocks frame technological demonstrating simulations acceptance architecture reuse initiate efficiency ips software dynamic bandwidth first memory building workloads blanc

Project "Mont-Blanc 2020" data sheet

The following table provides information about the project.

Coordinator	BULL SAS Organization address address: RUE JEAN JAURES 68 city: LES CLAYES SOUS BOIS postcode: 78340 website: www.bull.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.
Coordinator Country	France [FR]
Project website	http://www.montblanc-project.eu
Total cost	10˙131˙848 €
EC max contribution	10˙131˙848 € (100%)
Programme	1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT))
Code Call	H2020-ICT-2017-1
Funding Scheme	RIA
Starting year	2017
Duration (year-month-day)	from 2017-12-01 to 2020-11-30

Partnership

Take a look of project's partnership.

#	participants	country	role	EC contrib. [€]
1	BULL SAS BULL SAS Organization address address: RUE JEAN JAURES 68 city: LES CLAYES SOUS BOIS postcode: 78340 website: www.bull.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (LES CLAYES SOUS BOIS)	coordinator	3˙816˙743.00
2	COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES Organization address address: RUE LEBLANC 25 city: PARIS 15 postcode: 75015 website: www.cea.fr contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (PARIS 15)	participant	2˙049˙923.00
3	SEMIDYNAMICS TECHNOLOGY SERVICES SL SEMIDYNAMICS TECHNOLOGY SERVICES SL Organization address address: CALLE MUNTANER 447 PLANTA 4 PUERTA 1 city: BARCELONA postcode: 8021 website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	ES (BARCELONA)	participant	1˙700˙690.00
4	BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION Organization address address: Calle Jordi Girona 31 city: BARCELONA postcode: 8034 website: www.bsc.es contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	ES (BARCELONA)	participant	950˙000.00
5	ARM LIMITED ARM LIMITED Organization address address: 110 FULBOURN ROAD city: CAMBRIDGE postcode: CB1 9NJ website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (CAMBRIDGE)	participant	549˙887.00
6	FORSCHUNGSZENTRUM JULICH GMBH FORSCHUNGSZENTRUM JULICH GMBH Organization address address: WILHELM JOHNEN STRASSE city: JULICH postcode: 52428 website: www.fz-juelich.de contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	DE (JULICH)	participant	542˙060.00
7	KALRAY SA KALRAY SA Organization address address: 180 AVENUE DE L' EUROPE IMMEUBLE LE SUN city: MONTBONNOT postcode: 38330 website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (MONTBONNOT)	participant	458˙125.00
8	SIPEARL SIPEARL Organization address address: 64 RUE D ACHERES city: MAISONS LAFFITTE postcode: 78600 website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (MAISONS LAFFITTE)	participant	64˙418.00

Map

Project objective

The Mont-Blanc 2020 (MB2020) project ambitions to initiate the development of a future low-power European processor for Exascale. MB2020 lays the foundation for a European consortium aiming at delivering a processor with great energy efficiency for HPC and server workloads. A first generation product is scheduled in the 2020 time frame.

Our target is to reach exascale-level power efficiency (50 Gflops/Watt at processor level) with a second generation planned for 2022. Therefore, we will, within MB2020: 1. define a low-power System-on-Chip (SoC) implementation targeting Exascale, with built-in security and reliability features; 2. introduce strong innovations to improve efficiency with real-life applications and to outperform competition (vector instruction implementation, memory latency and bandwidth, power management, 2.5D integration); 3. develop key modules (IPs) needed for this implementation; 4. provide a working prototype demonstrating MB2020 key components and system level simulations, with a co-design approach based on real-life applications; 5. explore the reuse of these building blocks to serve other markets than HPC.

Our key choices are: a) To use the ARM ISA (Instruction Set Architecture) because its has strong technological relevance and it offers a dynamic ecosystem, which is needed to deliver the system software and applications mandatory for successful market acceptance. b) To design, implement or leverage new technologies (Scalable Vector Extension, NoC, High Bandwidth Memory, Power Management, …) as well as innovative packaging technologies to improve the versatility, performance, power efficiency, reliability, and security of the processor. c) To improve on the economic sustainability of processor development through a modular design that allows to retarget our SoC for different markets.

Deliverables

List of deliverables.
Set of (Mini) applications for HPC tests	Documents, reports	2020-03-24 00:38:54

Take a look to the deliverables list in detail: detailed list of Mont-Blanc 2020 deliverables.

Publications

List of publications.
year	authors and title	journal	last update
2019	Julien Adam, Maxime Kermarquer, Jean-Baptiste Besnard, Leonardo Bautista-Gomez, Marc PÃ©rache, Patrick Carribault, Julien Jaeger, Allen D. Malony, Sameer Shende Checkpoint/restart approaches for a thread-based MPI runtime published pages: 204-219, ISSN: 0167-8191, DOI: 10.1016/j.parco.2019.02.006	Parallel Computing 85	2020-03-24
2019	Kallia Chronaki, Miquel MoretÃ³, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard AyguadÃ©, Mateo Valero On the maturity of parallel applications for asymmetric multi-core processors published pages: 105-115, ISSN: 0743-7315, DOI: 10.1016/j.jpdc.2019.01.007	Journal of Parallel and Distributed Computing 127	2020-03-24
2018	Jaulmes, Luc; MoretÃ³, Miquel; Valero, Mateo; Casas, Marc Memory Vulnerability: A Case for Delaying Error Reporting published pages: , ISSN: , DOI:	1	2020-03-24
2018	Kallia Chronaki, Marc Casas, Miquel Moreto, Jaume Bosch, Rosa M. Badia TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism published pages: 389-409, ISSN: , DOI: 10.1007/978-3-319-92040-5_20	ISC 2018 Proceedings	2020-03-24

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The information about "MONT-BLANC 2020" are provided by the European Opendata Portal: CORDIS opendata.