Report

Teaser, summary, work performed and final results

Periodic Reporting for period 1 - MNEMOSENE (Computation-in-memory architecture based on resistive devices)

Teaser

Mass production and commercialization of technologies based on integrated circuits, such as computers and mobile phones, have completely revolutionized our society, ultimately resulting in the Digital Revolution and leading humanity into what is now referred to as the...

Summary

Mass production and commercialization of technologies based on integrated circuits, such as computers and mobile phones, have completely revolutionized our society, ultimately resulting in the Digital Revolution and leading humanity into what is now referred to as the Information Age.
Emerging electronic applications, such as Internet-of-Things and Big Data analytics, are expected to impact our lives even further, but they require increasing computing power with severe constraints on size, energy consumption and reliability. Current manufacturing technologies, electronic devices and computer architectures are unable to deliver the functionalities and features needed by these applications. In order to meet these challenging requirements and prepare the European electronics industry for the next generation of computing technologies, novel approaches have to be devised and implemented.
Computation-In-Memory (CIM) is a new computing paradigm, enabled by a new class of memory devices (often referred to as memristors), which allows for certain computational tasks to be performed in the memory itself and thus addressing several shortcomings of current architectures. MNEMOSENE will focus on the development, design and demonstration of a CIM architecture based on extending arrays of non-volatile resistive switching devices (memristors) with logic functionality inside or around the cell array. By allowing integration of information processing and storage at the same physical location, CIM architectures have the potential to (a) eliminate the communication and memory bottleneck, (b) support massive parallelism to increase the overall performance, (c) drastically enhance energy efficiency, and (d) be cheaper to manufacture.
To ensure impacts beyond the project timeframe, MNEMOSENE partners have foreseen a 9-12 year technology development roadmap that, starting from the integration of a CIM die with a conventional CPU on a single chip, will ultimately lead to a CIM-based computer.
From a technical / scientific standpoint, the following objectives will be targeted:
• Objective 1: Develop new algorithmic solutions for targeted applications for CIM architecture.
• Objective 2: Develop and design new mapping methods integrated in a framework for efficient compilation of the new algorithms into CIM macro-level operations; each of these is mapped to a group of CIM tiles.
• Objective 3: Develop a macro-architecture based on the integration of group of CIM tiles, including the overall scheduling of the macro-level operation, data accesses, inter-tile communication, the partitioning of the crossbar, etc.
• Objective 4: Develop and demonstrate the micro-architecture level of CIM tiles and their models, including primitive logic and arithmetic operators, the mapping of such operators on the crossbar, different circuit choices and the associated design trade-offs, etc.
• Objective 5: Design a simulator (based on calibrated models of memristor devices & building blocks) and FPGA emulator for the new architecture (CIM device combined with conventional CPU) in order demonstrate its superiority.

Work performed

In the first period (M1-M18), different tasks have been carried out according to the plan; all WP-specific objectives planned for this period have been achieved. The project is progressing very good, many excellent results have been achieved, and many concepts have been demonstrated.
• Applications have been defined analysed and kernels to be accelerated were identified, and new solutions targeting Computation-in-Memory (CIM) architecture (which is the topic of the project) were proposed.
• A high level (macro tiles) CIM architecture and its Instruction Set Architecture were defined and versions were developed; the integration of this CIM accelerator in existing computer cluster platform is ongoing. Part of the interfaces (to CIM core) were developed and others are in development.
• The building blocks of CIM macro tiles were designed and most of them were validated (others ongoing); these consist of memristor based circuits enabling computation-in-memory, nano-instruction set, compiler of macro to nano-instructions, etc. Version of CIM tile simulator is already produced.
• Version of the compiler being able to identify the kernels to be accelerated from high-level application code and compile them into instruction understood by the proposed architecture.
All of these are now being integrated in a final full system demonstrator to show the superiority of CIM architecture for the targeted applications.

Final results

\"MNEMOSENE targets a ground-breaking objective: the development and demonstration of a radically different computation architecture addressing major shortcomings of current technologies with respect to latency, energy consumption, area efficiency and scalability. MNEMOSENE is expected to deliver progress beyond the state of the art at all architectural levels, starting from the single memristive device up to a CIM demonstrator. At the nano-level, research will focus on a single crossbar memristor tile including control logic needed for operating the memristor cells to perform gate-level operations and memory reads and writes. At the micro-level, more elaborate control will be developed to perform basic operations like addition and multiplication, and also operations for input and output of data to and from a tile. Finally, at the macro-level, multiple CIM tiles will be interconnected, forming a complete CIM architecture capable of executing complete loop-nests and functions.
Innovations introduced in MNEOSENE are expected to reduce the memory/communication wall by orders of magnitude, provide huge scalable bandwidth, eliminate leakage and support massive parallelism, thus leading to the first architecture to really break the processor-memory wall. These ground-breaking objectives will not only enable efficient computation of currently hard/infeasible important societal applications (e.g., healthcare, data sciences, etc) but also enable novel applications towards (ultra) low power electronics such as Internet of Things (IoT).
By the end of the project, a demonstrator will be produced and tested to show that the storage and processing can be effectively integrated in the same physical location to improve energy efficiency and also to show that the proposed accelerator is able to achieve the following measurable targets (as compared with a general purpose multi-core platform) for the considered applications:
• Improve the energy-delay product by factor of 100X to 1000X
• Improve the computational efficiency (#operations / total-energy) by factor of 10X to 100X
• Improve the performance density (# operations per area) by factor of 10X to 100X

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Website & more info

More info: http://www.mnemosene.eu.