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Report

Teaser, summary, work performed and final results

Periodic Reporting for period 1 - Mont-Blanc 3 (Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology)

Teaser

Summary

Back in October 2011, the Mont-Blanc consortium launched the first phase of a project aimed at exploring an energy-efficient alternative to current supercomputers, based on low-power mobile processors, with the ambition of setting future HPC standards for the Exascale era. Six years later, the Mont-Blanc project has indeed given birth to a fully functional prototype that allowed project members to demonstrate the viability of using European embedded commodity technology for High Performance Computing. The project also defined a set of developer tools and ported real scientific applications to this new environment. More globally, the project has given good visibility to the concept of using mobile technology for HPC.

Today, energy efficiency is more than ever the primary concern for future Exascale systems, which confirms the relevance of the Mont-Blanc approach. The objective of the third phase of the Mont-Blanc project is to leverage the lessons learned during the first and second phases of the initiative. The project continues to take a holistic approach, encompassing hardware, operating system and tools, and applications, with the following targets:

- Defining the architecture of an Exascale-class compute node based on the ARM architecture, and capable of being manufactured at industrial scale;
- Assessing the available options for maximum compute efficiency;
- Developing the matching software ecosystem to pave the way for market acceptance of ARM solutions.

The third phase of the Mont-Blanc project â€“ launched in Oct. 2015 - is coordinated by Bull, the Atos brand for technology products and software, and has a budget of 7.9 million Euros, funded by the European Commission under the Horizon2020 program.

Work performed

At mid-term, the Mont-Blanc 3 project has already achieved significant results in all domains :
- The definition of an ARM based HPC test platform, integrating new ARM based compute blades in an existing HPC platform named Bull Sequana. Our SoC choice for this test platform, Cavium ThunderX2, has been announced in January 2017. This platform is now being built, for a deployment phased between Q3 2017 & Q1 2018.
- a multi-scale simulation workflow strategy has been defined and implemented through a first set of simulation tools enhancements.
- Alternative ways to get increased computation throughput while improving energy efficiency are explored via the evaluation of the main architectural trends within the HPC area and the analysis of ARMâ€™s Scalable Vector Extensions (SVE)
- An in-depth study of the applications of interest has been performed, and some initial testing done on available Mont-Blanc platforms
- Work on the software ecosystem has been pursued, and ARM is now part of OpenHPC 1.2

Final results

\"The potential impact is considerable: the Mont-Blanc project is an actor in the development of a European HPC technology.

As recognized by the EU Commission in IPCEI European Strategic Positioning Paper (November 2015), \"\"HPC, big data and ultra-fast internet access are enabling technologies for all European industrial sectors. Europe has a unique opportunity to act now and invest in the development and deployment of HPC technology, Big Data and Applications. Failure to do so will seriously undermine European competitiveness and Europe will miss an important opportunity to ensure its industries compete on a global level. \"\"
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