NeuRAM3 project deliverables
The page lists 10 deliverables related to the research project "NeuRAM3".
List of Deliverables
| title and desprition | type | last update |
|---|---|---|
Physical Level and Computational Level benchmarking.Physical Level and Computational Level benchmarking. Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Documents, reports | 2020-01-28 |
Toolbox of algorithms and computational architecture building blocks.Toolbox of algorithms and computational architecture building blocks. Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Other | 2020-01-28 |
Joint publication on hardware compatible recurrent neural network architecture.Joint publication on hardware compatible recurrent neural network architecture. Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Documents, reports | 2020-01-28 |
Report on spike-based learning circuits suitable for RRAM technologies.Report on spike-based learning circuits suitable for RRAM technologies. Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Documents, reports | 2020-01-28 |
Design ready for tape-out of the FDSOI 28nm multi-core spiking neural network chip.Design ready for tape-out of the FDSOI 28nm multi-core spiking neural network chip. Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Other | 2020-01-28 |
Project web-site on line with public and restricted areasProject web-site on line with public and restricted areas Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Other | 2020-01-28 |
Report on the characteristics of TFT’s as interconnects for a Global Synapse ChipsReport on the characteristics of TFT’s as interconnects for a Global Synapse Chips Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Documents, reports | 2020-01-28 |
Report on digital spike-based computing circuits suitable for RRAM technologiesReport on digital spike-based computing circuits suitable for RRAM technologies Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Documents, reports | 2020-01-28 |
Process description for the integration of RRAM technology in 28nm FDSOI BEOL, as input for WP 3Process description for the integration of RRAM technology in 28nm FDSOI BEOL, as input for WP 3 Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Documents, reports | 2020-01-28 |
Electrical characterization of 1T-1R RRAM cell as input for compact modeling for WP 2Electrical characterization of 1T-1R RRAM cell as input for compact modeling for WP2 Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015 |
Documents, reports | 2020-01-28 |