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Report

Teaser, summary, work performed and final results

Periodic Reporting for period 1 - DAHLIA (Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic)

Teaser

DAHLIA will target an innovative real-time System-on-Chip for space applications where mixed-criticalities between co-running applications will need to be guaranteed and where resources will be allocated in time and space to the running applications. Overall, the main...

Summary

DAHLIA will target an innovative real-time System-on-Chip for space applications where mixed-criticalities between co-running applications will need to be guaranteed and where resources will be allocated in time and space to the running applications. Overall, the main novelties of the project will be:
1. European None Dependence achieved through the use of European semiconductor technology and European IP technologies. The Consortium is made of key technology industrial partners.
2. Development of a Very High Performance microprocessor while achieving state-of-the-art real-time performances based on European 28nm FDSOI with multicore ARM processor for real time applications and a very large embedded FPGA device for flexibility support. The chip will be designed for the complete platform with 28 nm FDSOI technology offering outstanding intrinsic radiation robustness.
3. A common definition of the SoC between the main actors of the European Space Industry, targeting the largest scope of space applications, aiming in optimizing the development costs and leading to an increased competitiveness of the European Space Industry. DAHLIA System-on-Chip will contains the following main features:
• 4 x ARM Cortex-R52 with Debug & Trace
• SoC Services such as Clock & Reset management, Timers & Watchdog, Temperature & Voltage sensors, Secure Boot
• CCSDS On Board Time
• On-Chip Memories all protected by ECC
• External Memory interface supporting Non Volatile (Flash) and Volatile (DDR) memories with ECC
• Multi-channel DMA controller
• CCSDS TM & TC
• GNSS
• Wide range of communication links: SpW, 1553, UART, CAN, SPI, HSSL…
• Embedded FPGA for flexibility
4. Development of real-time support with the new ARM Cortex-R52 processors to cope with the mixed-criticalities of the co-running applications. The Cortex-R Series have been developed by ARM to offer performance for real-time applications. Within the Cortex-R family, the Cortex-R52 represents ARM’s most advanced processor in term of performances and safety.
5. The usage of the naturally immune to latchup STMicroelectronics 28nm FDSOI technology to implement the High performance Microprocessor.

Work performed

The first reporting period was dedicated to the project set-up and the beginning of the design phase both at IP and SoC top level stages:
1. SoC requirements have been defined and synthetized by Thales in a single document: deliverable “D4.1 – DAHLIA SoC Requirements Specification Document”. It specifies the functions, features and interfaces that the SoC must provide in order to give to the future users a SoC powerful enough and flexible to be effectively used in many different space applications (platform computers, payload computers, instrument control units, etc.) with different mission profiles (telecom, remote sensing, exploration, science). The document focus on ‘what’ the SoC must have, with few indications on ‘how’ to implement them. These specifications provides inputs for the subsequent architectural design of the SoC
2. The architecture of the SoC has been defined by the consortium with Airbus as a leader. The architecture definition has been done in two steps:
a. A high level architecture description: deliverable D5.1 – Preliminary SoC Architecture Description
b. A detailed architecture description: deliverable D5.2 - Final SoC Architecture Description
During this definition phase a particular focus has been put by NanoXplore on the FPGA bitstream security.
3. STMicroelectronics gave access to the consortium Access to its ARM IP licenses and to the 28FDSOI design environment.
4. Preliminary versions of almost all of the IPs that will be mapped in ASIC gates have been released.
5. A first version of the top level RTL is available and synthesis trials are ongoing to pipe clean the design flow.
6. The validation strategy has been completely reviewed and improved by ISD.
7. The DAHLIA project has been presented in 4 conferences. The details of the conferences are available on DAHLIA web site at http://dahlia-h2020.eu

Final results

The performance is expected to be 20 to 40 times the performance of the existing SoC for space and more than 2 times the performance of the future quad core LEON4 chip. This performance level, combined with a large set of integrated peripherals including dedicated on-chip functions for GNSS, TM and TC support, will enable key space applications to be executed within the same microprocessor significantly reducing cost and mass and boosting competitiveness of future European space equipment.
Considering the Cortex-R52 performance and the frequency achievable with the 28 nm technology, we can estimate the overall DAHLIA performance beyond 4000 DMIPS.

Website & more info

More info: http://dahlia-h2020.eu/.