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DESIGN-EID SIGNED

Defect Simulation and Material Growth of III-V Nanostructures- European Industrial Doctorate Program

Total Cost €

EC-Contrib. €

Partnership

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DESIGN-EID project word cloud

Explore the words cloud of the DESIGN-EID project. It provides you a very rough idea of what is the project "DESIGN-EID" about.

dislocations completely substrate integration secondly gap memory young qu financially function silicon exploited observing prediction shift defects esrs semiconductor overcome bits achievable evaluation first last desing nitrides pure cmos chip train whereas direct heterogeneous experimental eid tools eliminating significantly sensors vacancies extended photonic sic transport technological time designing predictive compound device electronic crystal framework performance combine semiconductors photonics inevitably minimizing simulation hence hybridisation materials accurate monolithic bridge si simulations decreases power

Project "DESIGN-EID" data sheet

The following table provides information about the project.

Coordinator	UNIVERSITY OF GLASGOW Organization address address: UNIVERSITY AVENUE city: GLASGOW postcode: G12 8QQ website: www.gla.ac.uk contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.
Coordinator Country	United Kingdom [UK]
Total cost	878˙988 €
EC max contribution	878˙988 € (100%)
Programme	1. H2020-EU.1.3.1. (Fostering new skills by means of excellent initial training of researchers)
Code Call	H2020-MSCA-ITN-2019
Funding Scheme	MSCA-ITN-EID
Starting year	2020
Duration (year-month-day)	from 2020-01-01 to 2023-12-31

Partnership

Take a look of project's partnership.

#	participants	country	role	EC contrib. [€]
1	UNIVERSITY OF GLASGOW UNIVERSITY OF GLASGOW Organization address address: UNIVERSITY AVENUE city: GLASGOW postcode: G12 8QQ website: www.gla.ac.uk contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (GLASGOW)	coordinator	336˙858.00
2	IBM RESEARCH GMBH IBM RESEARCH GMBH Organization address address: SAEUMERSTRASSE 4 city: RUESCHLIKON postcode: 8803 website: www.zurich.ibm.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	CH (RUESCHLIKON)	participant	343˙782.00
3	SYNOPSYS DENMARK APS SYNOPSYS DENMARK APS Organization address address: FRUEBJERGVEJ 3 city: COPENHAGEN V postcode: 1200 website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	DK (COPENHAGEN V)	participant	198˙348.00

Map

Project objective

In semiconductor technology and applications today, we are increasingly observing a shift from the pure silicon CMOS technology towards hybridisation of function in terms of bringing in sensors, power, memory and photonics functionality on the same chip. In particular, there is a great interest in the heterogeneous and monolithic integration of III-V materials and other complex semiconductors, such as III-Nitrides and SiC on Si substrate. However, the direct growth of III-V materials on silicon inevitably will lead to crystal defects that significantly decreases performance of novel devices.

To overcome this main technological challenge and to make this new technology financially viable, the most cost-effective and time-effective approach is to combine experimental and simulation work, which indeed is the main aim on this project – DESING-EID. This will be achieved by addressing the following objectives.

The first objective of DESIGN-EID is to train three young ESRs who will bridge the gap between predictive simulations, experimental materials and device development by developing simulation tools for prediction of crystal growth as a function of process conditions. Secondly, completely eliminating defects in compound semiconductors is likely not achievable, therefore a simulation framework providing an accurate evaluation of their impact on device performance will be essential for designing devices and materials minimizing their impact. Furthermore, semiconductor defects in semiconductors may be exploited for their unique electronic properties if their presence and properties are controlled. For example, vacancies might be used to implement Qu-bits, whereas extended defects, such as dislocations, can provide unique transport properties. Hence, the last objective of the DESIGN-EID project focuses on experimental control and accurate simulation of the impact of defects on electronic and photonic device performance.

Deliverables

List of deliverables.
Supervisory Board of the network	Other	2020-02-27 15:24:00

Take a look to the deliverables list in detail: detailed list of DESIGN-EID deliverables.

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