SUPERAID7
Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node
Total Cost €
0EC-Contrib. €
0Partnership
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0SUPERAID7 project word cloud
Explore the words cloud of the SUPERAID7 project. It provides you a very rough idea of what is the project "SUPERAID7" about.
Project "SUPERAID7" data sheet
The following table provides information about the project.
| Coordinator |
FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Organization address contact info |
| Coordinator Country | Germany [DE] |
| Project website | http://www.superaid7.eu |
| Total cost | 3˙377˙527 € |
| EC max contribution | 3˙377˙527 € (100%) |
| Programme |
1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)) |
| Code Call | H2020-ICT-2015 |
| Funding Scheme | RIA |
| Starting year | 2016 |
| Duration (year-month-day) | from 2016-01-01 to 2018-12-31 |
Partnership
Take a look of project's partnership.
| # | ||||
|---|---|---|---|---|
| 1 | FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V. | DE (MUNCHEN) | coordinator | 970˙600.00 |
| 2 | COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES | FR (PARIS 15) | participant | 621˙122.00 |
| 3 | UNIVERSITY OF GLASGOW | UK (GLASGOW) | participant | 598˙205.00 |
| 4 | TECHNISCHE UNIVERSITAET WIEN | AT (WIEN) | participant | 534˙250.00 |
| 5 | Gold Standard Simulations ltd | UK (Glasgow) | participant | 382˙877.00 |
| 6 | SYNOPSYS (NORTHERN EUROPE) LIMITED | UK (READING BERKSHIRE) | participant | 270˙472.00 |
Map
Project objective
Among the physical limitations which challenge progress in nanoelectronics for aggressively scaled More Moore, process variability is getting ever more critical. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fabricated, just by changing the corresponding input data. This important requirement for and capability of simulation is among others highlighted in the International Technology Roadmap for Semiconductors ITRS. SUPERAID7 will build upon the successful FP7 project SUPERTHEME which focused on advanced More-than-Moore devices, and will establish a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below, including especially interconnects. This will need improved physical models and extended compact models. Device architectures addressed in the benchmarks include especially TriGate/ΩGate FETs and stacked nanowires, including alternative channel materials. The software developed will be benchmarked utilizing background and sideground experiments of the partner CEA. Main channels for exploitation will be software commercialization via the partner GSS and support of device architecture activities at CEA. Furthermore, an Industrial Advisory Board initially consisting of GLOBALFOUNDRIES and STMicroelectronics will contribute to the specifications and will get early access to the project results.
Deliverables
| Hierarchical set of presentation foils and leaflets for use by SUPERAID7 partners and eventually by the EC services – to be updated until the end of the project | Documents, reports | 2019-10-02 12:46:27 |
| Final version of SUPERAID7 WWW including restricted section and including material from the SUPERAID7 Workshop | Websites, patent fillings, videos etc. | 2019-10-02 12:46:27 |
| Summary of results of SUPERAID7 dissemination actions (events, papers) | Documents, reports | 2019-10-02 12:46:27 |
| Guide to research data disseminated from SUPERAID7 | Open Research Data Pilot | 2019-10-02 12:46:27 |
| Public workshop on variability | Websites, patent fillings, videos etc. | 2019-10-02 12:46:27 |
| Demonstration of correlation-aware simulation of impacts of statistical and systematic variability | Documents, reports | 2019-10-02 12:46:27 |
| Publishable version of the Technology Implementation Plan | Documents, reports | 2019-10-02 12:46:27 |
| Set-up of SUPERAID7 WWW including preliminary version of restricted section | Websites, patent fillings, videos etc. | 2019-10-02 12:46:27 |
| Project Presentation | Websites, patent fillings, videos etc. | 2019-10-02 12:46:27 |
Take a look to the deliverables list in detail: detailed list of SUPERAID7 deliverables.
Publications
| year | authors and title | journal | last update |
|---|---|---|---|
| 2017 |
Talib Al-Ameri, Vihar P. Georgiev, Fikru Adamu-Lema, Asen Asenov Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications published pages: 466-472, ISSN: 2168-6734, DOI: 10.1109/jeds.2017.2752465 |
IEEE Journal of the Electron Devices Society 5/6 | 2019-10-02 |
| 2017 |
S. Barraud, V. Lapras, M. Samson, B. Previtali, J. Hartmann, N. Rambal, C. Vizioz, V. Loup, C. Comboroure, F. Triozon, N. Bernier, D. Cooper, M. Vinet Stacked-Wires FETs for Advanced CMOS Scaling published pages: 1, ISSN: , DOI: |
Proceedings 2017 International Conference on Solid State Devices and Materials (SSDM 2017) | 2019-10-02 |
| 2017 |
Zaiping Zeng, Francois Triozon, Sylvain Barraud, Yann-Michel Niquet A Simple Interpolation Model for the Carrier Mobility in Trigate and Gate-All-Around Silicon NWFETs published pages: 2485-2491, ISSN: 0018-9383, DOI: 10.1109/ted.2017.2691406 |
IEEE Transactions on Electron Devices 64/6 | 2019-10-02 |
| 2018 |
Juergen Klaus Lorenz, Asen Asenov, Eberhard Baer, Sylvain Barraud, Campbell Millar, Mihail Nedjalkov (Invited) Process Variability for Devices at and Beyond the 7 nm Node published pages: 113-124, ISSN: 1938-5862, DOI: 10.1149/08508.0113ecst |
ECS Transactions 85/8 | 2019-10-02 |
| 2018 |
Xaver Klemenschits, Siegfried Selberherr, Lado Filipovic Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review published pages: 631, ISSN: 2072-666X, DOI: 10.3390/mi9120631 |
Micromachines 9/12 | 2019-10-02 |
| 2018 |
Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs published pages: 62-70, ISSN: 0038-1101, DOI: 10.1016/j.sse.2018.08.012 |
Solid-State Electronics 149 | 2019-10-02 |
| 2019 |
Toufik Sadi, Cristina Medina-Bailon, Mihail Nedjalkov, Jaehyun Lee, Oves Badami, Salim Berrada, Hamilton Carrillo-Nunez, Vihar Georgiev, Siegfried Selberherr, Asen Asenov Simulation of the Impact of Ionized Impurity Scattering on the Total Mobility in Si Nanowire Transistors published pages: 124, ISSN: 1996-1944, DOI: 10.3390/ma12010124 |
Materials 12/1 | 2019-10-02 |
| 2017 |
Paul Ellinghaus, Josef Weinbub, Mihail Nedjalkov, Siegfried Selberherr Analysis of lense-governed Wigner signed particle quantum dynamics published pages: 1700102, ISSN: 1862-6254, DOI: 10.1002/pssr.201700102 |
physica status solidi (RRL) - Rapid Research Letters 11/7 | 2019-10-02 |
| 2019 |
Jürgen Lorenz, Eberhard Bär, Sylvain Barraud, Andrew Brown, Peter Evanschitzky, Fabian Klüpfel, Liping Wang Process Variability—Technological Challenge and Design Issue for Nanoscale Devices published pages: 6, ISSN: 2072-666X, DOI: 10.3390/mi10010006 |
Micromachines 10/1 | 2019-10-02 |
| 2018 |
Jaehyun Lee, Oves Badami, Hamilton Carrillo-Nuñez, Salim Berrada, Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Vihar Georgiev, Asen Asenov Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs published pages: 643, ISSN: 2072-666X, DOI: 10.3390/mi9120643 |
Micromachines 9/12 | 2019-10-02 |
| 2018 |
Mihail Nedjalkov, Paul Ellinghaus, Josef Weinbub, Toufik Sadi, Asen Asenov, Ivan Dimov, Siegfried Selberherr Stochastic analysis of surface roughness models in quantum wires published pages: 30-37, ISSN: 0010-4655, DOI: 10.1016/j.cpc.2018.03.010 |
Computer Physics Communications 228 | 2019-10-02 |
| 2018 |
J. K. Lorenz, A. Asenov, E. Baer, S. Barraud, F. Kluepfel, C. Millar, M. Nedjalkov Process Variability for Devices at and beyond the 7Â nm Node published pages: P595-P601, ISSN: 2162-8769, DOI: 10.1149/2.0051811jss |
ECS Journal of Solid State Science and Technology 7/11 | 2019-10-02 |
| 2018 |
Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello Electrical characterization of vertically stacked p-FET SOI nanowires published pages: 84-91, ISSN: 0038-1101, DOI: 10.1016/j.sse.2017.12.011 |
Solid-State Electronics 141 | 2019-10-02 |
| 2017 |
Vihar P. Georgiev, Muhammad M. Mirza, Alexandru-Iustin Dochioiu, Fikru Adamu-Lema, Salvatore M. Amoroso, Ewan Towie, Craig Riddet, Donald A. MacLaren, Asen Asenov, Douglas J. Paul Experimental and Simulation Study of Silicon Nanowire Transistors Using Heavily Doped Channels published pages: 727-735, ISSN: 1536-125X, DOI: 10.1109/tnano.2017.2665691 |
IEEE Transactions on Nanotechnology 16/5 | 2019-10-02 |
| 2018 |
Talib Al-Ameri Correlation between the Golden Ratio and Nanowire Transistor Performance published pages: 54, ISSN: 2076-3417, DOI: 10.3390/app8010054 |
Applied Sciences 8/1 | 2019-10-02 |
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