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REMINDER project deliverables

The page lists 19 deliverables related to the research project "REMINDER".

 List of Deliverables

REMINDER: list of downloadable deliverables.
title and desprition type last update

Description of the technical requirements for advanced process modules to be included in first run

Description of the technical requirements for advanced process modules
to be included in first run

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Compact models and assessment of the model accuracy based on comparison of simulation and measurement results

Linked to T4.2. The deliverable will contain the description of several compact models with different complexity and precision. These models will be obtained from the simplification of the semi-analytical model developed in T4.1 and explained in D4.1

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

FB-DRAM optimization for the first fabrication run

Linked with T3.1, T3.2 & T3.5: FB-DRAM optimization for the first fabrication run (WP1): determination of the architectures, bias conditions and technological parameters required to achieve best static (current level, power consumption) and dynamic (programming, reading and retention) performances.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Implementation of the novel FB-DRAM generic structures in 2D TCAD simulators.

Linked with T3.1 & T3.2) Implementation of the novel FB-DRAM generic structures in 2D TCAD simulators. Calibration/validation of the 2D/3D TCAD tools, with the physics parameters extracted in WP2, for simulation of the basic DC characteristics (drain and gate currents, body potential variation, etc.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Development of the simulation methodology for conducting detailed transient analysis and systematic results

Linked to T3.2. It will contain the simulation methodology and the results for the systematic study of the transient behavior of the different memory cells to reveal dynamic aspects related to programming, reading and retention. Transient TCAD simulations and refined Monte Carlo simulations will be used.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

REMINDER Data Management Plan

Linked to T6.2, Scientific dissemination and training. The purpose of the Data Management Plan (DMP) is to support the data management life cycle for all data that will be collected, processed or generated by the project. A DMP is a document outlining how research data will be handled during a research project, and after it is completed.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Technical requirements for the modelling platform

Linked with T4.1: Numerical and analytical modelling of transient body potential, injection mechanisms related to programming, leakage current relevant for the retention time and scaling effects. D4.1 will contain the equations and parameters of the model develop to take into account the dynamic behavior of a FB-DRAM.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

REMINDER web-site

Linked to T6.1. Website of REMINDER consortium
A project web-site will be set-up with a public area presenting the project objectives, work-plan, partners, main progress, and dissemination plan. A restricted area will also be available to project partners to give access to all documents produced in the course of the project and to provide a dedicated area for sharing scientific documents.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Websites, patent fillings, videos etc. 2019-08-30

FB-DRAM optimization for the second fabrication run

Linked with T3.1, T3.2 & T3.5: FB-DRAM optimization for the second fabrication run (WP1): determination of the architectures, bias conditions and technological parameters required to achieve best static (current level, power consumption) and dynamic (programming, reading and retention) performances.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Characterization of III-V nanowires and devices

This deliverable is linked to task T2.9, which is the characterization of III-V nanowires and devices fabricated in WP1. The deliverable summarizes the results obtained related to:
-III-V nanowire structural and electrical properties
-III-V nanowire device and module characterization

A first version of this deliverable will be launched at month 12, and upgraded versions will be elaborated at month 24 and month 36.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

First year technical report

Linked to T6.1. This deliverable will report on the activities developed and the outcomes achieved during the first year of the project.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Simulation of FB-DRAM variability using DOE and surface response techniques

This deliverable is linked to T3.4. It will contain the results of the analysis of the influence of the influence that the statistical variations of the technological parameters have on the performance of FB-DRAM cells (retention time,
current levels, power consumption, etc.). The variability aspects of memory circuit-design and manufacturability with accurate leakage models will be taken into account. Methods which enable detailed predictions of variability at the circuit-level without sacrificing total simulation time will be developed. Activities will focus on two types of variability simulations:
- Die-to-die variations.
-Intra-die variations and component mismatch.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Development of accurate models to describe band structure related effects in III-V nanowires.

Linked to T3.7. The deliverable will collect the results obtained on the advanced simulation of III-V nanowires, focusing on the detailed band structure description of III-V NWs including CB-VB interaction and strain.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Definition of the electrical parameters required by the simulation and modelling

This deliverable is linked to Task T2.1, development of measurement techniques ans setups to determine the key parameters and performance of FB-DRAMs. It will contain the information related to the specific outputs of the task:
-Definition of specific test structures based on the definition of all the electrical characteristics
needed for model extraction in close interaction with WP4 and WP1.
-Extraction of electrical and physics parameters relevant to transient effects in FB-DRAM (lifetime,
leakage currents, mobility, series resistance).
-Determination of the efficiency of the injection mechanisms for the ‘1’-state programming.
-Evaluation of the retention time based on transient measurements.
-Measurement of the impact of high temperature operation (> 80°C) on the retention time, programming speed, and current margins.
-Development of characterisation procedures to estimate the transient body potential variation by using direct (body contact) and indirect methods.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Extraction of the physics parameters needed in compact models and design

This deliverable is linked to task T2.6, and it is closely related to WP2, WP3 and WP4. The techniques developed in T2.1 will be applied to extract the parameters needed for fine tuning of compact and semi-analytical models. This deliverable will collect the results about:
- Carrier lifetime: determined with the measurement setup used for retention time characterization.
- Parameters of B2BT, impact ionization and bipolar transistor: temperature behaviour.
- Diffusion and depletion lengths: necessary for modelling junction leakage current and retention capability.
- Series resistance and carrier mobility: required for modelling the current levels and reading speed.
-Short-channel effects: needed to evaluate the limits of scalability

Four sets of devices will be considered along the life of the project:
run0 - Devices already avaliable
run1- First lot fabrication
run2- Second lot fabrication
run3- Third lot fabrication
After each run, the physics parameters will be extracted. Therefore, the deliverable will be updated every six months, after the first version in M12.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Development of new characterization techniques for the extraction of “transient” parameters and memory performance

This deliverable is linked to Task T2.2. The goal of the task is to quantify the memory mechanisms is various devices already available at the technological partners of the Consortium. The deliverable will contain the results of the outputs achieved:
-Probe the memory effect in various structures: (i) Scaled FD SOI MOSFETs, (ii) Double-gate FinFETs and nanowires.
- Measurement of the impact of high temperature operation on the retention time, programming speed, and current margins on the different devices.
- Provide inputs, which together with those of T2.3 and WP3, will guide the architecture design of devices to be fabricated in WP1 and models to be developed in WP4.
- Validation of simulation results obtained in WP3.
- Design of test pattern
- Design of test algorithm (testability, system, procedures of failure analysis)
- Electrical characteristic analysis (I-V, C-V)
- Physical characteristic analysis (Atomic Probe Tomography, SIMS, EXAF, RBS, EELS,
Stress/strain analysis)

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

CMOS Lot primary characterization

Electrical and structural characterization of the devices fabricated at the three programmed runs. This deliverable will content the results from Task T1.4. This task concerns the characterization of the processed memory devices. The statistical characterization carried out with industrial parametric probers (600 and 680 Keithley) aims to check the conformity of the full CMOS process with embedded 1T-DRAM. Thus the main technological parameters (dielectric thickness, sheet resistance, etc…) and electrical parameters (threshold voltage, current level in various regimes, etc…)
are statistically measured on each wafer for all geometries (gate length, channel width, etc…) implemented on the test vehicle. Analyses of these electrical measurements allow controlling the various process steps and

The first version of the deliverable will be submitted at M18 after the outcome of the first run. There will be upgraded versions after second run (M24) and after the third run M30.

Three sets of memory structures will be fabricated in CMOS FD28 and FD14 technology:
Run 1: Fabrication of optimized FB-DRAM solutions (selected after benchmarking of Run 0
devices) and first approach to the memory matrix.
Run 2: Results from the first run will educate the memory array design of the second run, which will
be limited to the optimized version of the best FB-DRAM variant. In addition, a second set of optimized FBDRAM
solutions will be fabricated, taking into account the results of the first run.
The devices and structures fabricated in WP1 will be carefully measured in WP2 and simulated in WP3, in
order to extract the parameters of the compact models developed in WP4.
Run 3: The data will be useful to define end-user applications using the optimized memory solution
and to fabricate the memory demonstrator in Run 3.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30

Plug and play library with advanced toolbox for integration of FB-DRAM devices

Linked to T4.3 and T4.4. A toolbox containing building blocks for a library of complex memory matrix array including the simplified models derived in T4.2 and T4.3. Models with variable complexity (temperature effects included) will be considered, from very simple/fast-computing models to advanced/slow-computing models. The models will be checked against measurements (WP2) and numerical simulations (WP3). For selected
devices, the models will be checked in simple demonstrators, memory matrix arrays fabricated in WP1.
The toolbox is aimed as a true ‘plug and play’ library which has a potential to be applied for all versions of FB-DRAMs. The toolbox will aim to be implemented into SPICE, ELDO, etc. The toolbox will allow the selection of particular FB-DRAM structure (e.g. single gate, double gate, multi-bodies, variable dimensional parameters, etc), operating conditions (e.g. bias, temperature), injection programming method (e.g. tunnelling, ionization, or bipolar), suited transistor model (semi-analytical or compact), and electro-thermal model. Using these models FBDRAM cell dynamics will be evaluated and explored feeding back results so the models may be optimised if necessary in order to ensure modelling accuracy in the commercial design environment.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Other 2019-08-30

Preliminary calibration of TCAD simulations based on parameters extracted in WP1 using pre-existing devices

The deliverable is linked to T3.1 and T3.2, and will collect the calibration results of TCAD simulations by comparing the simulated results with the parameters extracted in WP1 using pre-existing devices. The calibration will include both stationary and transient behaviour of the devices.

Programme: H2020-EU.2.1.1. - Topic(s): ICT-25-2015

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 Documents, reports 2019-08-30