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REMINDER SIGNED

Revolutionary embedded memory for internet of things devices and energy reduction

Total Cost €

EC-Contrib. €

Partnership

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Outcomes and
results

REMINDER project word cloud

Explore the words cloud of the REMINDER project. It provides you a very rough idea of what is the project "REMINDER" about.

voltage investigation chip techniques fd28 memory boosting cut floating point speed analysed immunity body fd14 materials consumption extreme solutions architectures tolerant behavioural demonstration tools internet dram strained blocks fdsoi smes si ideally eventual fabrication ultimate nanoelectronics replacement matrix simulation cells underpinned deep centers statistical fulfilment power cmos things reminder device solution ultra incorporating sige balanced evaluation performance optimization footprint subcircuits variability electrical cell redesign industrial nanometric characterization benchmarking nodes alternative supporting 28nm robustness circuits reliability view models universities carefully optimized nanoelectronic imply 14nm edge bit

Project "REMINDER" data sheet

The following table provides information about the project.

Coordinator	UNIVERSIDAD DE GRANADA Organization address address: CUESTA DEL HOSPICIO SN city: GRANADA postcode: 18071 website: www.ugr.es contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.
Coordinator Country	Spain [ES]
Project website	http://www.reminder2020.eu
Total cost	4˙543˙793 €
EC max contribution	3˙597˙418 € (79%)
Programme	1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT))
Code Call	H2020-ICT-2015
Funding Scheme	RIA
Starting year	2016
Duration (year-month-day)	from 2016-01-01 to 2019-06-30

Partnership

Take a look of project's partnership.

#	participants	country	role	EC contrib. [€]
1	UNIVERSIDAD DE GRANADA UNIVERSIDAD DE GRANADA Organization address address: CUESTA DEL HOSPICIO SN city: GRANADA postcode: 18071 website: www.ugr.es contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	ES (GRANADA)	coordinator	606˙250.00
2	COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES Organization address address: RUE LEBLANC 25 city: PARIS 15 postcode: 75015 website: www.cea.fr contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (PARIS 15)	participant	761˙596.00
3	STMICROELECTRONICS SA STMICROELECTRONICS SA Organization address address: BOULEVARD ROMAIN ROLLAND 29 city: MONTROUGE postcode: 92120 website: www.st.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (MONTROUGE)	participant	537˙500.00
4	INSTITUT POLYTECHNIQUE DE GRENOBLE INSTITUT POLYTECHNIQUE DE GRENOBLE Organization address address: AVENUE FELIX VIALLET 46 city: GRENOBLE CEDEX 1 postcode: 38031 website: http://www.grenoble-inp.fr contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	FR (GRENOBLE CEDEX 1)	participant	501˙385.00
5	SURECORE LTD SURECORE LTD Organization address address: FLOOR 5, 2 WELLINGTON PLACE city: LEEDS postcode: LS1 4AP website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (LEEDS)	participant	495˙750.00
6	UNIVERSITY OF GLASGOW UNIVERSITY OF GLASGOW Organization address address: UNIVERSITY AVENUE city: GLASGOW postcode: G12 8QQ website: www.gla.ac.uk contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (GLASGOW)	participant	350˙000.00
7	SYNOPSYS (NORTHERN EUROPE) LIMITED SYNOPSYS (NORTHERN EUROPE) LIMITED Organization address address: BROOK DRIVE 100 GREEN PARK city: READING BERKSHIRE postcode: RG2 6UJ website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (READING BERKSHIRE)	participant	185˙268.00
8	Gold Standard Simulations ltd Gold Standard Simulations ltd Organization address address: Mitchell Street 90 Gordon Chambers city: Glasgow postcode: G1 3NQ website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (Glasgow)	participant	159˙668.00
9	IBM RESEARCH GMBH IBM RESEARCH GMBH Organization address address: SAEUMERSTRASSE 4 city: RUESCHLIKON postcode: 8803 website: www.zurich.ibm.com contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	CH (RUESCHLIKON)	participant	0.00
10	Korea Institute of Science and Technology Korea Institute of Science and Technology Organization address address: 39-1 Hawolgok-Dong, Seongbuk-Gu city: Seoul postcode: 136-791 website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	KR (Seoul)	participant	0.00

Map

Project objective

REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption and variability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are : i) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness (variability), speed, reduced footprint and cost. ii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits, blocks and architectures will be carefully analysed from the power-consumption point of view. In addition variability tolerant design techniques underpinned by variability analysis and statistical simulation technology will be considered. iii) Demonstration of a system on chip application using the developed memory solution and benchmarking with alternative embedded memory blocks. The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also require the redesign of different applications, including memory cells, and therefore we also propose the evaluation of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative materials. The fulfilment of the objectives above will also imply the development of: i) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will allow us to improve the CMOS technology by boosting device performance. ii) New behavioural models, incorporating variability effects, to reach a deep understanding of nanoelectronics devices iii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices. iv) Extreme low power solutions The consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.

Deliverables

List of deliverables.
Description of the technical requirements for advanced process modules to be included in first run	Documents, reports	2019-08-30 14:06:07
Compact models and assessment of the model accuracy based on comparison of simulation and measurement results	Documents, reports	2019-08-30 14:06:08
FB-DRAM optimization for the first fabrication run	Documents, reports	2019-08-30 14:06:07
Implementation of the novel FB-DRAM generic structures in 2D TCAD simulators.	Documents, reports	2019-08-30 14:06:07
Development of the simulation methodology for conducting detailed transient analysis and systematic results	Documents, reports	2019-08-30 14:06:07
REMINDER Data Management Plan	Documents, reports	2019-08-30 14:06:09
Technical requirements for the modelling platform	Documents, reports	2019-08-30 14:06:08
REMINDER web-site	Websites, patent fillings, videos etc.	2019-08-30 14:06:09
FB-DRAM optimization for the second fabrication run	Documents, reports	2019-08-30 14:06:08
Characterization of III-V nanowires and devices	Documents, reports	2019-08-30 14:06:09
First year technical report	Documents, reports	2019-08-30 14:06:09
Simulation of FB-DRAM variability using DOE and surface response techniques	Documents, reports	2019-08-30 14:06:07
Development of accurate models to describe band structure related effects in III-V nanowires.	Documents, reports	2019-08-30 14:06:07
Definition of the electrical parameters required by the simulation and modelling	Documents, reports	2019-08-30 14:06:09
Extraction of the physics parameters needed in compact models and design	Documents, reports	2019-08-30 14:06:09
Development of new characterization techniques for the extraction of â€œtransientâ€ parameters and memory performance	Documents, reports	2019-08-30 14:06:09
CMOS Lot primary characterization	Documents, reports	2019-08-30 14:06:08
Plug and play library with advanced toolbox for integration of FB-DRAM devices	Other	2019-08-30 14:06:08
Preliminary calibration of TCAD simulations based on parameters extracted in WP1 using pre-existing devices	Documents, reports	2019-08-30 14:06:07

Take a look to the deliverables list in detail: detailed list of REMINDER deliverables.

Publications

List of publications.
year	authors and title	journal	last update
2018	S. Cristoloveanu, K.H. Lee, M.S. Parihar, H. El Dirani, J. Lacord, S. Martinie, C. Le Royer, J.-Ch. Barbe, X. Mescot, P. Fonteneau, Ph. Galy, F. Gamiz, C. Navarro, B. Cheng, M. Duan, F. Adamu-Lema, A. Asenov, Y. Taur, Y. Xu, Y-T. Kim, J. Wan, M. Bawedin A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters published pages: 10-19, ISSN: 0038-1101, DOI: 10.1016/j.sse.2017.11.012	Solid-State Electronics 143	2020-02-05
2018	Carlos Navarro, Santiago Navarro, Carlos Marquez, Luca Donetti, Carlos Sampedro, Siegfried Karg, H. Riel, Francisco Gamiz InGaAs Capacitor-Less DRAM Cells TCAD Demonstration published pages: 884-892, ISSN: 2168-6734, DOI: 10.1109/jeds.2018.2859233	IEEE Journal of the Electron Devices Society 6/1	2020-02-05
2019	C. Navarro, S. Navarro, C. Marquez, J. L. Padilla, P. Galy, F. Gamiz 3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z 2 -FETs published pages: 2513-2519, ISSN: 0018-9383, DOI: 10.1109/ted.2019.2912457	IEEE Transactions on Electron Devices 66/6	2020-02-05
2018	Santiago Navarro, Carlos Navarro, Carlos Marquez, Hassan El Dirani, Philippe Galy, Maryline Bawedin, Andy Pickering, Sorin Cristoloveanu, Francisco Gamiz Experimental Demonstration of Operational Z 2 -FET Memory Matrix published pages: 660-663, ISSN: 0741-3106, DOI: 10.1109/led.2018.2819801	IEEE Electron Device Letters 39/5	2020-02-05
2017	Yuan Taur, Joris Lacord, Mukta Singh Parihar, Jing Wan, Sebastien Martinie, Kyunghwa Lee, Maryline Bawedin, Jean-Charles Barbe, Sorin Cristoloveanu A comprehensive model on field-effect pnpn devices (Z 2 -FET) published pages: 1-8, ISSN: 0038-1101, DOI: 10.1016/j.sse.2017.05.004	Solid-State Electronics 134	2019-10-29
2017	Carlos Navarro, Joris Lacord, Mukta Singh Parihar, Fikru Adamu-Lema, Meng Duan, Noel Rodriguez, Binjie Cheng, Hassan El Dirani, Jean-Charles Barbe, Pascal Fonteneau, Maryline Bawedin, Campbell Millar, Philippe Galy, Cyrille Le Royer, Siegfried Karg, Paul Wells, Yong-Tae Kim, Asen Asenov, Sorin Cristoloveanu, Francisco Gamiz Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM published pages: 4486-4491, ISSN: 0018-9383, DOI: 10.1109/ted.2017.2751141	IEEE Transactions on Electron Devices 64/11	2019-08-30
2017	Carlos Navarro, Meng Duan, Mukta Singh Parihar, Fikru Adamu-Lema, Stefan Coseman, Joris Lacord, Kyunghwa Lee, Carlos Sampedro, Binjie Cheng, Hassan El Dirani, Jean-Charles Barbe, Pascal Fonteneau, Seong-Il Kim, Sorin Cristoloveanu, Maryline Bawedin, Campbell Millar, Philippe Galy, Cyrille Le Royer, Siegfried Karg, Heike Riel, Paul Wells, Yong-Tae Kim, Asen Asenov, Francisco Gamiz ${Z}^{textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration published pages: 4904-4909, ISSN: 0018-9383, DOI: 10.1109/ted.2017.2759308	IEEE Transactions on Electron Devices 64/12	2019-08-30
2017	H. El Dirani, K.H. Lee, M.S. Parihar, J. Lacord, S. Martinie, J-Ch. Barbe, X. Mescot, P. Fonteneau, J.-E. Broquin, G. Ghibaudo, Ph. Galy, F. Gamiz, Y. Taur, Y.-T. Kim, S. Cristoloveanu, M. Bawedin Ultra-low power 1T-DRAM in FDSOI technology published pages: 245-249, ISSN: 0167-9317, DOI: 10.1016/j.mee.2017.05.047	Microelectronic Engineering 178	2019-08-30

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