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Report

Teaser, summary, work performed and final results

Periodic Reporting for period 2 - In-Need (III-Nitrides Nanostructures for Energy-Efficiency Devices)

Teaser

The main goal of this project is to demonstrate a completely new platform based on nanostructures that will enable to optimally exploit the outstanding properties of GaN semiconductors for state-of-the-art electronic devices. The properties of this class of semiconductors...

Summary

The main goal of this project is to demonstrate a completely new platform based on nanostructures that will enable to optimally exploit the outstanding properties of GaN semiconductors for state-of-the-art electronic devices. The properties of this class of semiconductors yield a larger Baliga’s figure of merit than in other materials, such as SiC and Si, enabling high-efficiency and miniaturized power devices operating at higher temperature (reducing cooling requirements), and high frequencies (reducing inductive elements in power circuits). However, the current performance of III-Nitride devices is far from the fundamental materials limit. For power switching applications, it has been very challenging to address concurrently all the main requirements for an efficient device, such as the ability to hold large blocking voltages while maintaining very low leakage current in off-state and very small resistance (RON) in on-state; Normally-off operation; Efficient thermal management to allow larger power densities; and high reliability.

To address these challenges, this proposal is divided into three overall objectives:
• SP-A. Surface nanostructures for unprecedented lateral device performance
• SP-B. Embedded nanostructures for new vertical devices
• SP-C. Embedded nanostructures for advanced thermal management

This project has a significant importance to our society in the field of efficient usage of energy. Energy efficiency offers a vast and low-cost energy resource to address the increasing energy demand,
reduce carbon dioxide emissions, and enable the concurrent development of renewable energy technologies. Power electronic devices are at the heart of an efficient energy management required in any sustainable energy technology. They will play a pivotal role in energy efficiency with a potential to reduce by more than 20% the overall electricity consumption. The In-Need proposes a unique approach to address concurrently the challenges to make efficient power electronic devices based on this high-performance semiconductors by developing advanced nanostructures to exploit locally and optimally their superior properties. Nanostructuring distinct regions of the device will allow a precise control over their intrinsic characteristics. Efficient thermal management will be achieved with ultra-near junction cooling. Nano/micro-channels filled with high thermal conductivity materials or coolants will be embedded inside the device.
We believe our judicious nano-scale design of new high-performing materials will result in state-ofthe- art devices, leading to a large-scale impact in energy efficiency. The miniaturization and large power density enabled by our approach will allow future integration of power devices into single power microchips. This will revolutionize energy use much like Silicon microchips did for information processing.

Work performed

• SP-A. Surface nanostructures for unprecedented lateral device performance
In this work package, we have developed the following
1) High-performance tri-gate GaN power MOSHEMTs. Tri-gate architectures are very attractive for GaN power transistors, however, it increases the on-resistance due to the partial removal of carriers in the tri-gate region. More importantly, its potential for high-voltage power applications has not yet been understood nor demonstrated. To address these issues, we eliminated the increase in on-resistance in typical tri-gate GaN transistors by optimizing the tri-gate geometry, and then integrated a field plate into the transistors by forming the tri-gate structure within a conventional planar gate, demonstrating successfully high-voltage tri-gate GaN-on-Si power transistors as high-performance power switches. The tri-gate MOSHEMTs exhibited a reduced OFF-state leakage current (IOFF) and subthreshold slope (SS), an increased the ON/OFF ratio, and an improved the breakdown voltage (VBR). With a gate-to-drain separation (LGD) of 5 µm, the tri-gate MOSHEMTs exhibited VBR of 792 V at IOFF of 0.3 µA/mm, along with a very small specific on-resistance (RON,SP) of 0.91 ± 0.08 mΩ·cm2. With LGD of 15 µm, hard VBR of 1755 V at IOFF of 45 µA/mm with high soft VBR of 1370 V at IOFF = 1 µA/mm was achieved, showing the excellent potential of the tri-gate architecture for power transistors.

2) High-voltage and low-leakage tri-anode GaN power SBDs. GaN SBDs are promising as power rectifiers, and are also crucial for future efficient all-in-GaN power ICs. However, the major challenge is their poor voltage-blocking performance, as they usually present small breakdown voltage and very large reverse leakage current. To achieve high-voltage GaN SBDs and complete the family of GaN power devices, we proposed a model to address the challenge by controlling the pinch-off voltage of the field plate to fix the reverse voltage drop at the Schottky junction at small values. We used tri-anode and tri-gate as means to adjust the pinch-off voltage, and demonstrated tri-anode GaN-on-Si power SBDs with state-of-the-art performances. The tri-anode SBDs presented a small turn-on voltage (VON) of 0.76 ± 0.05 V, very low IR below 10 and 100 nA/mm at large reverse biases up to 500 and 700 V, respectively. In addition, these devices exhibited record VBR up to 1325 V at IR of 1 μA/mm (till the date of publication), rendering an excellent high power figure-of-merit (FOM) of 0.94 GW/cm2. Later we further improved these values and present new records as will be introduced in the following part.

3) Novel slanted tri-gate architecture for high-voltage GaN MOSHEMTs and SBDs. Field plates are usually needed for high-voltage GaN power devices, which however rely on a vertical scheme to tailor their properties by adjusting the type and thickness of the dielectric layer, making it extremely challenging to realize the optimal design of slant field plates. Here we invented a novel slanted tri-gate architecture, which spreads the electric field in a similar way as the slant filed but is fabricated in a much easier and more controllable way by simply tuning the width of the tri-gate lithographically. This approach provides a new degree of freedom for engineering the distribution of electric field, based on which we successfully demonstrated both high-voltage GaN-on-Si power MOSHEMTs and SBDs that outperformed the state-of-the-art. The slanted tri-gate GaN MOSHEMTs presented an increase of ~500 V in VBR compared to the counterpart planar devices, resulting in a high VBR of 1350 V at IOFF = 1 µA/mm with a small LGD of 10 μm, rendering a record high-power figure-of-merit (FOM) of 1.2 GW/cm2 among GaN-on-silicon lateral transistors (till the date of publication). The slanted tri-gate SBDs exhibited a record-low IR of 51 ± 5.9 nA/mm at -1000 V and a record-high VBR of -2000 V at 1 μA/mm (till now), rendering an excellent figure-or-merit of 1.16

Final results

\"• SP-A. Surface nanostructures for unprecedented lateral device performance: With the novel tri-gate and slanted tri-gate technologies developed in this work, we have demonstrated many GaN power devices with state-of-the-art performance, which are summarized as below.
1) The highest high power figure-of-merit (1.2 GW/cm2) for GaN-on-Si transistors using the slanted tri-gate technology [J. Ma and E. Matioli, IEEE Electron Device Letters 38, 1305 (2017).].
2) The highest VBR (-2000 V at 1 μA/mm) and the smallest IR (5 nA at -650 V) for GaN-on-Si SBDs, using the slanted tri-gate technology [J. Ma and E. Matioli, Applied Physics Letters 112, 052101 (2018)].
3) The smallest RON for GaN-on-Si transistors with VBR larger than 500 V, which is extremely promising for low-voltage power applications (≤ 200 V) [J. Ma and E. Matioli, IEEE Electron Device Letters 38, 367 (2017)].
4) The highest reverse VBR (-900 V at 1 μA/mm) and the lowest IR (20 nA/mm at -700 V) for reverse-blocking GaN transistors using the tri-anode technology [J. Ma, M. Zhu, and E. Matioli, IEEE Electron Device Letters 38, 1704 (2017)].
5) The highest VBR (1100 V at μA/mm), the lowest RON (8.83 Ω·mm) and the smallest VON (0.55 V) for reverse-conduction GaN transistors using the tri-anode technology [T. Wang, J. Ma and E. Matioli, IEEE Electron Device Letters 39, 1038 (2018)].
6) First demonstration of multi-channel tri-gate for ultra-low resistance electronics:
J. Ma, G. Kampitsis, P. Xiang, K. Cheng and E. Matioli, “Multi-Channel Tri-gate GaN Power Schottky Diodes with Low ON-Resistance”; IEEE Electron Device Letters, vol. 40, no. 2, pp. 275-278, 2018.
J. Ma, C. Erine, P. Xiang, K. Cheng and E. Matioli, “Multi-channel tri-gate normally-on/off AlGaN/GaN MOSHEMTs on Si substrate with high breakdown voltage and low ON-resistance”, Applied Physics Letters, 113, 24, 242102, 2018.
The ultimate objective of this project is to combine the superior potential of the tri-gate technologies in enhancing the VBR and the ultra-small resistance of multi-channel AlGaN/GaN heterostructures to deliver novel multi-channel tri-gate GaN power devices that outperform the state-of-the-art. Currently, we are optimizing the epitaxial growth of multi-channel heterostructures to yield high breakdown voltages. We have demonstrated ultra-low on-resistances using these concepts and our final goal is to demonstrate high voltages together with this.

• SP-B. Embedded nanostructures for new vertical devices
1.) We achieved an ultra-low on-resistance (Ron,sp) of 0.33 mΩcm2 , breakdown voltage (BV) of 820 V and a BFOM of 2.0 GW/cm2, all of which are state of the art performance reported to date in GaN-on-Si p-i-n diodes [R. A. Khadar; C. Liu; L. Zhang; P. Xiang; K. Cheng and E. Matioli, IEEE Electron Device Letters 39, 3, p. 401-404, 2018]. (choosen as editor pick of IEEE Electron Device Letters, in january 2018)
2.) We reported the first GaN-on-Si vertical transistor. The VBoff of 645 V and RON,SP of 6.8 mA· cm2 resulted in a very good Baliga figure-of-merit (FOM) of 61 MW/cm2, which is superior than devices fabricated on sapphire substrates [C. Liu; R. Abdul Khadar; E. Matioli, IEEE Electron Device Letters., 39, 1, p. 71, 2018]. (featured in the online magazine \"\"Semiconductor Today\"\" on 18th, January 2018)
3.) We reported for the first time monolithic integration of GaN vertical MOSFETs and freewheeling SBD. The integrated GaN-on-Si vertical SBDs reveal state-of-the-art performance, compared to vertical GaN-on-Si SBDs [C. Liu; R. Abdul Khadar; E. Matioli, IEEE Electron Device Letters., 39, 7, p. 1034, 2018]. (featured in the online magazine \"\"Semiconductor Today\"\" on 29th, June, 2018)
4.) We have demonstrated the first fully-vertical GaN-on-Si MOSFETs, with low specific on-resistance and high off-state breakdown voltage [R. A. Khadar, C. Liu, R. Soleimanzadeh, and E. Matioli, “Fully-vertical GaN-on-Si power MOSFETs”, IEEE Electron Device Letters, Vol. 40, issue 3, 443-446,\"