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Report

Teaser, summary, work performed and final results

Periodic Reporting for period 1 - Mont-Blanc 2020 (Mont-Blanc 2020, European scalable, modular and power efficient HPC processor)

Teaser

Summary

One of the main challenges of European HPC today is that Europe does not produce some of the key technologies for HPC, and particularly processors. Being able to design HPC systems based on home-grown technologies is critical for Europeâ€™s strategic self-reliance, as well as for the robustness of European industry and of the European job market.
The newly-created EuroHPC addresses this issue, promoting the development of European technology for the Exascale. As part of this, the European Processor Initiative (EPI) ambitions to deliver an indigenous HPC processor, as well as an embedded processor for automotive and other AI applications by 2025.
Mont-Blanc 2020 is upstream of EPI. The objective of Mont-Blanc 2020 is to start developing building blocks (IPs) for an HPC processor. The team will design and demonstrate ASIC modules, and this IP will be reused and productized within EPI. In that sense, EPI will rely on the work done in the Mont-Blanc 2020 project.

Work performed

\"During the period, the co-design approach helps to define the global architecture. A set of representative applications have been selected and a rich simulation methodology is available using both Gem5 modelling and virtual prototyping. In addition to the simulations, the inputs from the Rhea processor specification from EPI project have also been integrated to prepare the milestone MS1: HPC requirements listed

The Gem5 model is described in D4.1: SVE-enabled GEM5. The model with abstract power equations is available and has been described in D4.2. The porting of applications has started as expected thanks to these models. The milestone MS2 \"\" Integrate SVE into tracing tools\"\" is formally reached as the SVE-enabled Gem5 models is internally available and the applications porting has started. The milestone has been completed with the delivery of D4.2.

In the same time, the High Level Architecture Specifications (HAS) providing the features of the Network on Chip (NoC), the HBM memory controller and the power manager (CPM) have been produced as expected. These documents are capturing the requirements and will allow to start the design and validation tasks. It is used both by the designers for developing the described components and by architects for integration at processor level. First, the NoC IP specification and features list were available since M12 for the start of design and validation tasks. The deliverable D5.2: NoC IP high level architecture specification has been produced in M14. Then, the specifications of the two other IPs are also available for the start of design and validation tasks as planned. D5:3 HBM and CPM Controller High Level Architecture Specifications has been produced. These IPs are optimized when used together including innovative functions. The milestone MS3 \"\"New SoC IPs specifications\"\" is reached with the delivery of D5.2.

To demonstrate performance and functionality, the project will deliver a prototype implementation in RTL for some of its key components on an emulation platform. During this period, the end to end flow from applications traces to the emulator has been detailed and validated to anticipate as much as possible the tasks are mostly planned at the end of the project. The methodology requires the development of specific trace injectors which mimics compute units: SVE engine or accelerators. The SVE trace generator is defined and has produced the deliverable D4.4. The trace format allows the implementation of all required features and is ready for enhancements such as SVE power states or performance counters.

The requirements for other markets have been visited in the deliverable D6.1: Real-time and embedded requirements for MB2020 SoC. The other markets addressed are the high-performance embedded computing applications, the compute-intensive functions found in the perception unit of autonomous vehicles such as automobile and drones. This deliverable has been revisited. The specific requirements will be applied to the MB2020 IPs and the necessary additions or modifications will be inferred. The required adaptations of the delivered IPs are not included in the scope of this project, but the architecture of the IPs should ease their addition for future reuse.\"

Final results

The main objectives of the project are:
1. to define a low-power System-on-Chip architecture targeting Exascale;
2. to implement new critical building blocks (IPs) and provide a blueprint for its first generation implementation;
3. to deliver initial proof-of-concept demonstration on real life applications;
4. to explore the reuse of the building blocks to serve other markets than HPC