Report

Teaser, summary, work performed and final results

Periodic Reporting for period 1 - OCEAN12 (Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node)

Teaser

\"OCEAN12 is a major “Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node\"\" and leverage Europe leadership on Automotive and aeronautics applications.Since the last few years, electronic components become more and more prevalent in...

Summary

\"OCEAN12 is a major “Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node\"\" and leverage Europe leadership on Automotive and aeronautics applications.
Since the last few years, electronic components become more and more prevalent in the automotive industry. Today they create a superior value for the final customer and represent an important vector of differentiation in this industry. The share economy model, which drives innovation strategies in Smart mobility, will further increase the need for safe, cost efficient, secure, reliable and un-hackable operations, raising logically the proportion of electronics and software as a percentage of the total cost of a vehicle.
OCEAN12 aims to bring very concrete technological solutions and corresponding demonstrators to the key societal challenge of Smart mobility. Based on the innovative FDSOI technology, OCEAN12 will develop new processors and applications design that leverage Fully Depleted Silicon On Insulator (FD-SOI) technology to offer the industry’s lowest power consuming processor and components, especially for automotive and aeronautic applications.
OCEAN12 will develop a technology platform benefitting from FDSOI design’s extreme low leakage and operating voltage (Vdd) scalability attained thank to reverse and forward body biasing (RBB/FBB) of the integrate circuit and its power system architecture. This high performance, low power solution will enable the next strategic generations of smart vehicles. This platform will rely on:
• a pilot line facility capable to manufacture advanced substrates compatible with 12FDX technology,
• the definition of path finding solutions to push 12FDX technology performances and substrates solutions for innovative sensors,
• the development of innovative designs at the forefront of state of the art to enhance FDSOI capacity and guarantee the highest level of integrated solutions,
• the manufacturing of high performance ICs using all palette of FDSOI technologies,
The produced highly integrated, reliable, ultra-low power and lower cost components will be integrated in complex embedded systems accessible to TIER-1, 2 and OEMs and answering strategic challenges of future autonomous vehicles generations (land or air). Several product demonstrators are targeted: high end microcontroller plug and play board, high performance sensors data fusion, highly integrated low power video processing, awaking systems.
A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and secure a unique FDSOI roadmap beyond the 22FDX.
OCEAN 12 finally highlights Europe’s unique leading position on FDSOI technology integrating the entire manufacturing chain in this dynamic, from substrate suppliers and foundries to TIER-1 and OEM, involving academia and RTO’s.\"

Work performed

WP1: Grant and NDA signed, PCA discussions ongoing. 1st amendment proposed and validated.
Kick off successfully held in Soitec on September 27th 2018. Second consortium meeting held in Munich on June 26th 2019.
Important dissemination with 42 cumulated action realized by all partners along the value chain. A sharepoint enables a fast exchange and a collaborative work between all partners and a Website is proposed to amplify the project impact.

WP2:
T2.1, GF defined Next Generation substrate targets to support 22FD and beyond roadmap (D2.1). Focusing on SOI thickness variability performance, Soitec developed a Gen 1+ version of 22FDSOI SmartCut process, which exhibits significant (up to 22% thickness control) improvements (D2.2). Gen 1+ samples have been delivered to GF for evaluation purpose (Deliverable D2.3). SOI thickness variability, surface defect density and wafer geometry improvements are followed-up in order to match with device yield and advanced lithography performance.
Leti & EVG plan to finalize the development, installation and qualification of the new bonding tool in Leti in the next period. Finally Thales used high resolution TEM to analyse edges of wafer, with focus on SOI interfaces. The aim of these analyses should allow reducing overall wafer’s defectivity and targeting the best process choices. Such characterization activity closed the loop with above mentioned process optimization.
T2.2, a benchmark of the different possible solutions to boost device performance has been conducted and 5 axes identified: SiN layer stress, MOL contact, self aligned stressor, BOX creep and relaxation of SiGe.
A First SOI substrate on epi based donor was realized by LETI/SOITEC. Process building blocks studies such as splitting with improved dynamic and bonding with plasma were launched.

WP3:
T3.1 High-Performance Computing - Kalray: a first prototype of OpenVX on MPPA, simulation of MPPA core and investigation of IP requirements for GF technology started
T3.2 Power Management, Efficiency, and Optimization - EKUT: Implementation of hardware-level switching strategy in power management synthesis framework.
T3.3 Analog and Mixed-Signal - CEA/Fhg: A state of the art analysis of the frequency reference has been established. For CT ADC a new architecture has been proposed. An architecture study of the state-of-the-art high-speed ADCs was performed for OFDM radar SoC Version 2 (after amd 1)
T3.4 Transceiver Building Blocks - Bosch: Concept Design for RF, baseband and digital blocks was completed by Bosch. FPGA setup conception for validation board was started and update of PDK version (FhG). Many specifications were released
T3.5 Design Methodology and Automation - Muneda: First version of a failure analysis for digital circuits with promising results & Extension of schematic porting to handle additional terminal of cells in target technology and their wiring

WP4:
Elaboration of the component specifications and the definition of the (sub)system architectures for specific use-cases.
T4.1, Always on / awakening system: state of the art analysis including power consumption realized for RF based wake-up (CEA / TUD)
Set up of a demonstrator, including a MEMS prototype outside microphone proposed by Bosch for Sound based wakeup,
T4.2, Development of the concept for the digital signal processing for the Radar SoC (Bosch, FhG-EMFT) as well as the architecture for all digital building blocks and external interfaces,
T4.3, Elaboration of the 3rd generation of Coolidge processor and start of the validation by Kalray, in collaboration with GF. Full specification defined and detailed architecture completed for the new generation of high end microcontroller/microprocessor (ST).

WP5: Definition of the specific use cases, of the necessary conditions and constraints, experimental platform testing, and some first prototype preparation.
A workshop organized by AUDI in April 2019 enabled definition of the demonstrators and improved collaborat

Final results

FDSOI substrates developed in terms of uniformity and defectgivity,
Process and metrology technologies including plasma bonding and DRM,
Shock based and sound based always on wake up systems,
1st fast-chirp Radar chip in 22FDX technology,
New SW framework (KaF, Kalray Framework) and innovative neural network approach (KaNN, Kalray Neural Networks) for the high efficiency embedded computing design solution,

Website & more info

More info: https://www.drgateway.com/ocean12/servlet/catalog.