HARPA
Harnessing Performance Variability
| Coordinatore | POLITECNICO DI MILANO
Organization address
address: Via Ponzio 34/5 contact info |
| Nazionalità Coordinatore | Italy [IT] |
| Totale costo | 3˙979˙620 € |
| EC contributo | 2˙797˙000 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2013-10 |
| Funding Scheme | CP |
| Anno di inizio | 2013 |
| Periodo (anno-mese-giorno) | 2013-09-01 - 2016-08-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
POLITECNICO DI MILANO
Organization address
address: Via Ponzio 34/5 contact info |
IT (Milano) | coordinator | 0.00 |
| 2 |
HENESIS S.R.L.
Organization address
address: via Gramsci contact info |
IT (Boretto) | participant | 0.00 |
| 3 |
INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS
Organization address
address: Patission Str. contact info |
EL (ATHINA) | participant | 0.00 |
| 4 |
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Organization address
address: Kapeldreef contact info |
BE (LEUVEN) | participant | 0.00 |
| 5 |
STMICROELECTRONICS GRENOBLE 2 SAS
Organization address
address: RUE JULES HOROWITZ contact info |
FR (GRENOBLE) | participant | 0.00 |
| 6 |
THALES COMMUNICATIONS & SECURITY SAS
Organization address
address: AVENUE DES LOUVRESSES contact info |
FR (GENNEVILLIERS) | participant | 0.00 |
| 7 |
UNIVERSITY OF CYPRUS
Organization address
address: KALLIPOLEOS STREET contact info |
CY (NICOSIA) | participant | 0.00 |
| 8 |
VYSOKA SKOLA BANSKA - TECHNICKA UNIVERZITA OSTRAVA
Organization address
address: 17 Listopadu contact info |
CZ (OSTRAVA) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
Application requirements, power, and technological constraints are driving the architectural convergence of future processors towards heterogeneous many-cores. This development is confronted with variability challenges, mainly the susceptibility to time-dependent variations in silicon devices. Increasing guard-bands to battle variations is not scalable, due to the too large worst-case cost impact for technology nodes around 10 nm. The goal of HARPA is to enable next-generation embedded and high-performance heterogeneous many-cores to cost-effectively confront variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. The HARPA solution employs a cross-layer approach. A middleware implements a control engine that steers software/hardware knobs based on information from strategically dispersed monitors. This engine relies on technology models to identify/exploit various types of platform slack - performance, power/energy, thermal, lifetime, and structural (hardware) - to restore timing guarantees and ensure the expected lifetime amidst time-dependent variations. Dependable-Performance is critical for embedded applications to provide timing correctness; for high-performance applications, it is paramount to ensure load balancing in parallel phases and fast execution of sequential phases. The lifetime requirement has ramifications on the manufacturing process cost and the number of field-returns. The HARPA novelty is in seeking synergies in techniques that have been considered virtually exclusively in the embedded or high-performance domains (worst-case guaranteed partly proactive techniques in embedded, and dynamic best-effort reactive techniques in high-performance). HARPA will demonstrate the benefits of merging concepts from these two domains by evaluating key applications from both segments running on embedded and high-performance platforms.