MERASA
Multi-core Execution of Hard-real-time Applications Supporting Analysability
| Coordinatore | UNIVERSITAET AUGSBURG
Organization address
city: AUGSBURG contact info |
| Nazionalità Coordinatore | Germany [DE] |
| Totale costo | 3˙001˙703 € |
| EC contributo | 2˙100˙000 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2007-1 |
| Funding Scheme | CP |
| Anno di inizio | 2007 |
| Periodo (anno-mese-giorno) | 2007-11-01 - 2010-10-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
UNIVERSITAET AUGSBURG
Organization address
city: AUGSBURG contact info |
DE (AUGSBURG) | coordinator | 0.00 |
| 2 |
BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: CALLE JORDI GIRONA 31 contact info |
ES (BARCELONA) | participant | 0.00 |
| 3 |
HONEYWELL INTERNATIONAL SRO
Organization address
address: V PARKU CHODOV contact info |
CZ (PRAHA) | participant | 0.00 |
| 4 |
RAPITA SYSTEMS LIMITED
Organization address
address: ITCENTER,YORK SCIENCE PARK,HESLINGTON YORK contact info |
UK (YORK) | participant | 0.00 |
| 5 |
UNIVERSITE PAUL SABATIER TOULOUSE III
Organization address
address: ROUTE DE NARBONNE 118 contact info |
FR (TOULOUSE CEDEX 9) | participant | 0.00 |
Mappa
Word cloud
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
Obiettivo del progetto (Objective)
The increasing demand for functionality in current and future real-time embedded systems is driving an increase in performance of processors. However at the same time, in developing safety-related real-time embedded systems, there is a need to prove that the timing requirements are met. Multi-core processors are increasingly being considered as the solution to achieve the increased processor performance, without increasing CPU clock speeds and maintaining low chip costs, low power consumption etc. However, current trends in mainstream multi-core processor design result in processors with certainly reduced average execution times, but typically with unpredictable and unanalysable (or extremely pessimistic) worst case behaviour that deems them unusable in the domain of safety-related real-time embedded systems.nThe MERASA project will develop multi-core processor designs (from 2 to 16 cores) for hard real-time embedded systems hand in hand with timing analysis techniques and tools to guarantee the analysability and predictability regarding timing of every single feature provided by the processor. Design exploration activities will be performed in conjunction with the timing analysis tools. The project will address both static WCET analysis tools (the OTAWA toolset) as well as hybrid measurement-based tools (RapiTime) and their interoperability. It will also develop system-level software with predictable timing performance.nTo constrain production costs and technology integration risks, we investigate hardware-based real-time scheduling solutions that empower the same multi-core processor to handle hard, soft, and non real-time tasks on different cores. The developed hardware/software techniques will be evaluated by application studies from aerospace, automotive, and construction-machinery areas performed by selected industrial partners.