Coordinatore | BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Barcelona Supercomputing Center. Edificio Nexus II. Jordi Gi 29 contact info |
Nazionalità Coordinatore | Spain [ES] |
Totale costo | 2˙603˙890 € |
EC contributo | 1˙800˙000 € |
Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
Code Call | FP7-ICT-2009-4 |
Funding Scheme | CP |
Anno di inizio | 2010 |
Periodo (anno-mese-giorno) | 2010-02-01 - 2013-07-31 |
# | ||||
---|---|---|---|---|
1 |
BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Barcelona Supercomputing Center. Edificio Nexus II. Jordi Gi 29 contact info |
ES (Barcelona) | coordinator | 0.00 |
2 |
AIRBUS OPERATIONS SAS
Organization address
address: ROUTE DE BAYONNE contact info |
FR (TOULOUSE) | participant | 0.00 |
3 |
INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE
Organization address
address: Domaine de Voluceau, Rocquencourt contact info |
FR (LE CHESNAY Cedex) | participant | 0.00 |
4 |
RAPITA SYSTEMS LIMITED
Organization address
address: ITCENTER,YORK SCIENCE PARK,HESLINGTON YORK contact info |
UK (YORK) | participant | 0.00 |
5 |
UNIVERSITA DEGLI STUDI DI PADOVA
Organization address
address: Via VIII Febbraio contact info |
IT (PADOVA) | participant | 0.00 |
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
There is an ever-increasing demand both for new functionality and for reduced development and production costs for all kinds of Critical Real-Time Embedded (CRTE) systems (safety, mission or business critical). Moreover, new functionality demands can only be delivered by more complex software and aggressive hardware acceleration features like memory hierarchies and multicore processors. However, these greatly increase system complexity, making it much more difficult to analyse applications for their temporal behaviour. Another key problem of CRTE systems is the need to prove that they operate correctly, satisfying all temporal constraints. The current generation of platforms, despite being based on comparatively simple and old processor technologies, are already extremely difficult to analyse for their temporal behaviour, and resulting errors in operation, cost EU industries billions of Euros annually in warranty and post-production costs.nnThe PROARTIS thesis is that the timing behaviour of systems that use advanced hardware features like multicore CPUs and complex memory hierarchies can be analysed effectively by probabilistic timing analysis techniques that reduce the risk of temporal pathological cases to quantifiably negligible levels. Preliminary research results in cache replacement policies by members of the PROARTIS consortium strongly support this claim. PROARTIS defines new hardware and software architecture paradigms based on the concept of randomisation that, with minimal changes to current processes and methods, guarantee timing behaviours that can be analysed with probabilistic techniques. PROARTIS uses a holistic approach in which probabilistic analysis extends from hardware design, compiler and real time operating system to applications. On top of this platform, we will build probabilistic timing analysis methods based on current commercial tools. We will validate our approach via an industrial case study.
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