Explore the words cloud of the WAYTOGO FAST project. It provides you a very rough idea of what is the project "WAYTOGO FAST" about.
The following table provides information about the project.
Coordinator |
STMICROELECTRONICS CROLLES 2 SAS
Organization address contact info |
Coordinator Country | France [FR] |
Total cost | 99˙399˙264 € |
EC max contribution | 25˙796˙579 € (26%) |
Programme |
1. H2020-EU.2.1.1.7. (ECSEL) |
Code Call | ECSEL-2014-2 |
Funding Scheme | ECSEL-IA |
Starting year | 2015 |
Duration (year-month-day) | from 2015-05-01 to 2017-12-31 |
Take a look of project's partnership.
The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.
year | authors and title | journal | last update |
---|---|---|---|
2015 |
J. Widieza, F. Mazena, J-M. Hartmanna, Y. Bogumilowicza, E. Augendrea, C. Veytizoub, S. Solliera, M. Martinc, M-C. Rourea, V. Loupa, C. Euvrada, A. Seignarda, T. Baronc, R. Ciproc, F. Bassanic, A-M. Papona, C. Guedja, I. Huyetb, M. Rivoirea, P. Bessona, C. Figuetb, W. Schwarzenbachb, D. Delpratb and T. Signamarcheixa “High Mobility Materials on Insulator for Advanced Technology Nodes†published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
Theano A. Karatsori, Christoforos G. Theodorou, Xavier Mescot, Sebastien Haendler, Nicolas Planes, Gerard Ghibaudo, Charalabos A. Dimitriadis Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements published pages: 1-7, ISSN: 0018-9383, DOI: 10.1109/TED.2016.2583504 |
IEEE Transactions on Electron Devices | 2019-09-04 |
2016 |
L. Gerlich, M. Wislicenus, B. Uhlig, S. Riedel, R. Liske Cobalt MOCVD as a Flexible Process in Semiconductor Industry published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
Cristina Medina-Bailon, Jose L. Padilla, Carlos Sampedro, Cem Alper, Francisco Gamiz, Adrian Mihai Ionescu Implementation of Band-to-Band Tunneling Phenomena in a Multisubband Ensemble Monte Carlo Simulator: Application to Silicon TFETs published pages: 3084-3091, ISSN: 0018-9383, DOI: 10.1109/TED.2017.2715403 |
IEEE Transactions on Electron Devices 64/8 | 2019-09-04 |
2017 |
T. Lim et al. “Slow-wave coplanar strip line based Low-power 80-GHz Voltage Control Oscillator on 22-nm FDSOI technology,†published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
C.Maleville “Designing with FD-SOI Technologies†published pages: , ISSN: , DOI: |
2019-09-04 | |
2015 |
J.L. Rouviere, Y. Martin, N. Bernier, M. Vigouroux, D. Cooper, J.M. Zuo Using Electron Diffraction Techniques, CBED and N-PED to measure Strain with High Precision and High Spatial Resolution published pages: 2209-2210, ISSN: 1431-9276, DOI: 10.1017/S1431927615011824 |
Microscopy and Microanalysis 21/S3 | 2019-09-04 |
2017 |
M. Czernohorsky, K. Seidel, K. Kühnel, J. Niess, N. Sacher, W. Kegel, W. Lerch High-K metal gate stacks with ultra-thin interfacial layers formed by low temperature microwave-based plasma oxidation published pages: 262-265, ISSN: 0167-9317, DOI: 10.1016/j.mee.2017.05.041 |
Microelectronic Engineering 178 | 2019-09-04 |
2015 |
Y. Y. Wang, D. Cooper, J. Rouviere, C.E. Murray, N. Bernier, J. Bruley Nanoscale Strain Mapping in Embedded SiGe Devices by Dual Lens Dark Field Electron Holography and Precession Electron Diffraction published pages: 1963-1964, ISSN: 1431-9276, DOI: 10.1017/S1431927615010594 |
Microscopy and Microanalysis 21/S3 | 2019-09-04 |
2015 |
J. Kunkel “Designing with FD-SOI“ & “Interconnected Worldâ€. published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
P.Flatresse The FDSOI history and its future published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
F.Buchali Preemphased Prime Frequency Multicarrier Bases ENOB Assessment and its Application for Optimizing a Dual-Carrier 1-Tb/s QAM Transmitter published pages: , ISSN: , DOI: |
2019-09-04 | |
2015 |
T. Piliszczuk “Engineered substrates for low-power devices†published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
C.Mazure Keynote - The FDSOI saga published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
B.-Y. Nguyen, M.Sadaka, G.Gaudin, W. Schwarzenbach, K.Boudelle,C.Figuet and C.Maleville “Beyond Silicon CMOS: Progress and challenges†published pages: , ISSN: , DOI: |
2019-09-04 | |
2014 |
M. P. Vigouroux, V. Delaye, N. Bernier, R. Cipro, D. Lafond, G. Audoit, T. Baron, J. L. Rouvière, M. Martin, B. Chenevier, F. Bertin Strain mapping at the nanoscale using precession electron diffraction in transmission electron microscope with off axis camera published pages: 191906, ISSN: 0003-6951, DOI: 10.1063/1.4901435 |
Applied Physics Letters 105/19 | 2019-09-04 |
2015 |
G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, S. Cristoloveanu and C. Mazure “Investigation of Hot Carrier reliability of SOI and sSOI transistors using Back Bias†published pages: , ISSN: , DOI: |
2019-09-04 | |
2015 |
Nguyen, S. Barraud, L. Hutin, C. Tabone, F. Glowacki, J.-M. Hartmann, M.-P. Samson†, L. Ecarnot, B.-Y. Nguyen¤, C. Maleville, C. Mazuré, O. Faynot, M. Vinet “P-FET Co-Integration on Si and Strained SiGe Dual Channel Substrates Obtained by Ge Local Enrichment Technique†published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
L. Fauquier, B. Pelissier, D. Jalabert, F. Pierre, J.M. Hartmann, F. Rozé, D. Doloy, D. Le Cunff, C. Beitia, T. Baron Benefits of XPS nanocharacterization for process development and industrial control of thin SiGe channel layers in advanced CMOS technologies published pages: 105-110, ISSN: 1369-8001, DOI: 10.1016/j.mssp.2016.10.028 |
Materials Science in Semiconductor Processing 70 | 2019-09-04 |
2017 |
Yoann Blancquaert, Nivea Figueiro, Thibault Labbaye, Francisco Sanchez, Stephane Heraud, Roy Koret, Matthew Sendelbach, Ralf Michel, Shay Wolfling, Stephane Rey, Laurent Pain Scatterometry control for multiple electron beam lithography published pages: 101451F, ISSN: , DOI: 10.1117/12.2261389 |
Metrology, Inspection, and Process Control for Microlithography XXXI | 2019-09-04 |
2015 |
David Cooper, Nicolas Bernier, Jean-Luc Rouvière Combining 2 nm Spatial Resolution and 0.02% Precision for Deformation Mapping of Semiconductor Specimens in a Transmission Electron Microscope by Precession Electron Diffraction published pages: 5289-5294, ISSN: 1530-6984, DOI: 10.1021/acs.nanolett.5b01614 |
Nano Letters 15/8 | 2019-09-04 |
2015 |
L. Gaben, S. Barraud, P. Pimenta-Barros, Y. Morand, J. Pradelles, M.-P. Samson, B. Previtali, P. Besson, F. Allain, S. Monfray, F. Boeuf, T. Skotnicki, F. Balestra3 and M. Vine Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm channel pitch and opportunities for stacked-Nanowires architectures published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
Licinius Benea, Maryline Bawedin, Cécile Delacour, Irina Ionica Out-of-equilibrium body potential measurements in pseudo-MOSFET for sensing applications published pages: , ISSN: 0038-1101, DOI: 10.1016/j.sse.2017.11.010 |
Solid-State Electronics | 2019-09-04 |
2015 |
A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, J.-M. Pédini, A. Roule, D. Marseilhan, P. Besson, D. Rouchon, N. Bernier, C. Tabone, C. Plantier, M. Vinet, A New Method to Induce Local Tensile Strain in SOI Wafers: First Strain Results of the “BOX Creep†Technique†published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
A.Durand Characterization and industrial control of local stress in microelectronics: - Applications to advanced transistors technology of 20 nm published pages: , ISSN: , DOI: |
2019-09-04 | |
2013 |
G. Kozlowski, O. Fursenko, P. Zaumseil, T. Schroeder, M. Vorderwestner, P. Storck (Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers published pages: 613-621, ISSN: 1938-5862, DOI: 10.1149/05009.0613ecst |
ECS Transactions 50/9 | 2019-09-04 |
2016 |
A DURAND, M KAUFLING, D LE-CUNFF, D ROUCHON, P GERGAUDÂ Fast and Accurate solution of inverse problem for in-line monitoring of strain field determined by High Resolution X-Ray Diffraction Reciprocal Space Mapping published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
J. Widiez, C. Veytizou, J.-M. Hartmann, V. Loup, P. Besson, N. Baumel, C. Figuet, I. Huyet, F. Mazen, W. Schwarzenbach, C. Tempesta, L. Ecarnot 300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut Technology published pages: 79-88, ISSN: 1938-5862, DOI: 10.1149/07508.0079ecst |
ECS Transactions 75/8 | 2019-09-04 |
2016 |
A. Bonnevialle, S. Reboh, C. Le Royer, Y. Morand, J.-M. Hartmann, D. Rouchon, J.-M. Pedini, C. Tabone, N. Rambal, A. Payet, C. Plantier, F. Boeuf, M. Haond, A. Claverie, M. Vinet Localized STRASS Technique on Advanced FDSOI Platform: Highly Tensile Si Demonstration for Dual Strain CMOS Integration published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
Mirjana Videnovic-Misic Class AB Base-Band Amplifier Design with Body Biasing in 28nm UTBB FD-SOI CMOS published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
P.Gupta Advanced CMOS Nodes (FDSOI, FinFET) usage for High Reliability Markets from Device and Design published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
K. Kühnel, S. Riedel, W. Weinreich, X. Thrun, M. Czernohorsky, B. Pätzold, M. Rudolph Catalytic ALD of SiO2 as spacer for an E-Beam direct write self-aligned double patterning process on 300 mm wafers published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
Guerric de Streel, Francois Stas, Thibaut Gurne, Francois Durant, Charlotte Frenkel, Andreia Cathelin, David Bol SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping published pages: 1163-1177, ISSN: 0018-9200, DOI: 10.1109/JSSC.2016.2645607 |
IEEE Journal of Solid-State Circuits 52/4 | 2019-09-04 |
2015 |
N. Kernevez “How innovation and eco-system in Europe can enable future requirements in automotive electronics†published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
C.Maleville “Substrate maturity+D61:M61+D61:M61 and readiness in large volume to support mass adoption of ULP FDSOI platforms†published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
F. Andrieu, R. Berthelon, R. Boumchedda, G. Tricaud, L. Brunet, P. Batude, B. Mathieu, E. Avelar, A. Ayres de Sousa, G. Cibrario, O. Rozeau, J. Lacord, O. Billoint, C. Fenouillet-Béranger, S. Guissi, D. Fried, P. Morin, J.P. Noel, B. Giraud, S. Thuries, F. Arnaud, M. Vinet Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
W. Schwarzenbach, F. Allibert, C. Figuet, C. Girard and C. Maleville “Material and Device Innovation for Cost Effective CMOS Scaling Beyond 28nm†published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata Insights on the Body Charging and Noise Generation by Impact Ionization in Fully Depleted SOI MOSFETs published pages: 5093-5098, ISSN: 0018-9383, DOI: 10.1109/TED.2017.2762733 |
IEEE Transactions on Electron Devices 64/12 | 2019-09-04 |
2017 |
N. Ben Salem, R.K. Gupta “High Sigma Functional Qualification for Flipflops using MunEDA WiCkeD,†published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
J.-L. Rouviere, B. Haas, E. Robin, D. Cooper, N. Bernier, M. Williamson The Measurement of Strain, Chemistry and Electric Fields by STEM based Techniques published pages: 1414-1415, ISSN: 1431-9276, DOI: 10.1017/S1431927617007735 |
Microscopy and Microanalysis 23/S1 | 2019-09-04 |
2017 |
Andreia Cathelin Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration published pages: 18-26, ISSN: 1943-0582, DOI: 10.1109/MSSC.2017.2745738 |
IEEE Solid-State Circuits Magazine 9/4 | 2019-09-04 |
2016 |
M. Wislicenus, T. Martin, L. Gerlich, B. Uhlig Selective Area Deposition of MOCVD Co for BEOL Capping Applications published pages: , ISSN: , DOI: |
2019-09-04 | |
2016 |
W. Lerch, N. Sacher, W. Kegel, J. Niess, M. Czernohorsky Oxidation of Germanium at Low-temperature by Plasma Enhanced Processing published pages: , ISSN: , DOI: |
2019-09-04 | |
2018 |
C. Landesberger et al. “Novel chip embedding and interconnection technology for mm-wave System-in-Package (SiP) applications,†published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
Theano A. Karatsori, Christoforos G. Theodorou, Emmanuel Josse, Charalabos A. Dimitriadis, G. Ghibaudo All Operation Region Characterization and Modeling of Drain and Gate Current Mismatch in 14-nm Fully Depleted SOI MOSFETs published pages: 2080-2085, ISSN: 0018-9383, DOI: 10.1109/TED.2017.2686381 |
IEEE Transactions on Electron Devices 64/5 | 2019-09-04 |
2017 |
Aurèle Durand, Melissa Kaufling, Delphine Le-Cunff, Denis Rouchon, Patrice Gergaud In-line monitoring of strain distribution using high resolution X-ray Reciprocal space mapping into 20 nm SiGe pMOS published pages: 99-104, ISSN: 1369-8001, DOI: 10.1016/j.mssp.2016.12.003 |
Materials Science in Semiconductor Processing 70 | 2019-09-04 |
2017 |
C.Maleville Designing wit FD-SOI technologies published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
N.Daval SU3200 use case to enable Angström level FDSOI uniformity all wafers all points published pages: , ISSN: , DOI: |
2019-09-04 | |
2017 |
Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata Systematic method for electrical characterization of random telegraph noise in MOSFETs published pages: 115-120, ISSN: 0038-1101, DOI: 10.1016/j.sse.2016.10.031 |
Solid-State Electronics 128 | 2019-09-04 |
2017 |
R. Berthelon, F. Andrieu, S. Ortolland, R. Nicolas, T. Poiroux, E. Baylac, D. Dutartre, E. Josse, A. Claverie, M. Haond Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14nm UTBB FDSOI technology published pages: 72-79, ISSN: 0038-1101, DOI: 10.1016/j.sse.2016.10.011 |
Solid-State Electronics 128 | 2019-09-04 |
2016 |
David Cooper, Thibaud Denneulin, Nicolas Bernier, Armand Béché, Jean-Luc Rouvière Strain mapping of semiconductor specimens with nm-scale resolution in a transmission electron microscope published pages: 145-165, ISSN: 0968-4328, DOI: 10.1016/j.micron.2015.09.001 |
Micron 80 | 2019-09-04 |
2016 |
Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Rafael Ruiz, Akiko Ohata Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation published pages: 60-65, ISSN: 0038-1101, DOI: 10.1016/j.sse.2015.11.022 |
Solid-State Electronics 117 | 2019-09-04 |
2015 |
C. Marquez, N. Rodriguez, J. M. Montes, R. Ruiz, F. Gamiz, C. Sampedro, A. Ohata Direct Characterization of Impact Ionization Current in Silicon-on-Insulator Body-Contacted MOSFETs published pages: 93-99, ISSN: 1938-5862, DOI: 10.1149/06605.0093ecst |
ECS Transactions 66/5 | 2019-09-04 |
2016 |
W. Lerch, T. Schick, N. Sacher, W. Kegel, J. Niess, M. Czernohorsky, S. Riedel (Invited) Low-Temperature Microwave-Based Plasma Oxidation of Ge and Oxidation of Silicon Followed by Plasma Nitridation published pages: 101-114, ISSN: 1938-5862, DOI: 10.1149/07204.0101ecst |
ECS Transactions 72/4 | 2019-09-04 |
2016 |
Walter Schwarzenbach, Bich-Yen Nguyen, Frederic Allibert, Christophe Girard, Christophe Maleville Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability published pages: 2-9, ISSN: 0038-1101, DOI: 10.1016/j.sse.2015.11.008 |
Solid-State Electronics 117 | 2019-09-04 |
2017 |
A.S.N. Pereira, G. de Streel, N. Planes, M. Haond, R. Giacomini, D. Flandre, V. Kilchytska An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models published pages: 67-71, ISSN: 0038-1101, DOI: 10.1016/j.sse.2016.10.017 |
Solid-State Electronics 128 | 2019-09-04 |
2016 |
C. Medina-Bailon, C. Sampedro, F. Gámiz, A. Godoy, L. Donetti Impact of non uniform strain configuration on transport properties for FD14+ devices published pages: 232-236, ISSN: 0038-1101, DOI: 10.1016/j.sse.2015.08.013 |
Solid-State Electronics 115 | 2019-09-04 |
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The information about "WAYTOGO FAST" are provided by the European Opendata Portal: CORDIS opendata.