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EXTRA

Exploiting eXascale Technology with Reconfigurable Architectures

Total Cost €

EC-Contrib. €

Partnership

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Outcomes and
results

EXTRA project word cloud

Explore the words cloud of the EXTRA project. It provides you a very rough idea of what is the project "EXTRA" about.

flexible techniques architecture architectures nodes hardware times run truly specialized accelerated technologies efficient start fast exascale create bit prepare reconfigurable performance chain phases grain joint covers reduce compute tools exploration overhead blocks re fundamental ultra optimized idea leadership building improvements co synthesis hpc edge tuned computing complete platform handle heterogeneous implementations faster maximally extra time competitive coarse suggestions power optimally stringent optimization reconfiguration levels intrinsic

Project "EXTRA" data sheet

The following table provides information about the project.

Coordinator	UNIVERSITEIT GENT Organization address address: SINT PIETERSNIEUWSTRAAT 25 city: GENT postcode: 9000 website: http://www.ugent.be contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.
Coordinator Country	Belgium [BE]
Project website	http://extrahpc.eu
Total cost	3˙989˙931 €
EC max contribution	3˙989˙930 € (100%)
Programme	1. H2020-EU.1.2.2. (FET Proactive)
Code Call	H2020-FETHPC-2014
Funding Scheme	RIA
Starting year	2015
Duration (year-month-day)	from 2015-09-01 to 2018-08-31

Partnership

Take a look of project's partnership.

#	participants	country	role	EC contrib. [€]
1	UNIVERSITEIT GENT UNIVERSITEIT GENT Organization address address: SINT PIETERSNIEUWSTRAAT 25 city: GENT postcode: 9000 website: http://www.ugent.be contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	BE (GENT)	coordinator	530˙296.00
2	IMPERIAL COLLEGE OF SCIENCE TECHNOLOGY AND MEDICINE IMPERIAL COLLEGE OF SCIENCE TECHNOLOGY AND MEDICINE Organization address address: SOUTH KENSINGTON CAMPUS EXHIBITION ROAD city: LONDON postcode: SW7 2AZ website: http://www.imperial.ac.uk/ contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (LONDON)	participant	559˙080.00
3	UNIVERSITEIT VAN AMSTERDAM UNIVERSITEIT VAN AMSTERDAM Organization address address: SPUI 21 city: AMSTERDAM postcode: 1012WX website: www.uva.nl contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	NL (AMSTERDAM)	participant	533˙836.00
4	RUHR-UNIVERSITAET BOCHUM RUHR-UNIVERSITAET BOCHUM Organization address address: UNIVERSITAETSSTRASSE 150 city: BOCHUM postcode: 44801 website: www.rub.de contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	DE (BOCHUM)	participant	476˙250.00
5	POLITECNICO DI MILANO POLITECNICO DI MILANO Organization address address: PIAZZA LEONARDO DA VINCI 32 city: MILANO postcode: 20133 website: www.polimi.it contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	IT (MILANO)	participant	451˙250.00
6	TELECOMMUNICATION SYSTEMS INSTITUTE TELECOMMUNICATION SYSTEMS INSTITUTE Organization address address: Technical University of Crete Campus - Kounoupidiana city: CHANIA postcode: 73100 website: www.tsi.gr contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	EL (CHANIA)	participant	420˙000.00
7	MAXELER TECHNOLOGIES LIMITED MAXELER TECHNOLOGIES LIMITED Organization address address: 3 & 4 ALBION PLACE city: LONDON postcode: W6 0QT website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (LONDON)	participant	415˙000.00
8	SYNELIXIS LYSEIS PLIROFORIKIS AUTOMATISMOU & TILEPIKOINONION ANONIMI ETAIRIA SYNELIXIS LYSEIS PLIROFORIKIS AUTOMATISMOU & TILEPIKOINONION ANONIMI ETAIRIA Organization address address: FARMAKIDOU 10 city: CHALKIDA postcode: 34100 website: n.a. contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	EL (CHALKIDA)	participant	305˙812.00
9	THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE Organization address address: TRINITY LANE THE OLD SCHOOLS city: CAMBRIDGE postcode: CB2 1TN website: www.cam.ac.uk contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	UK (CAMBRIDGE)	participant	298˙406.00

Map

Project objective

To handle the stringent performance requirements of future exascale High Performance Computing (HPC) applications, HPC systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require reconfiguration as an intrinsic feature, so that specific HPC application features can be optimally accelerated at all times, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in from the start. The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future. The project EXTRA covers the complete chain from architecture up to the application: • More coarse-grain reconfigurable architectures that allow reconfiguration on higher functionality levels and therefore provide much faster reconfiguration than at the bit level. • The development of just-in time synthesis tools that are optimized for fast (but still efficient) re-synthesis of application phases to new, specialized implementations through reconfiguration. • The optimization of applications that maximally exploit reconfiguration. • Suggestions for improvements to reconfigurable technologies to enable the proposed reconfiguration of the architectures. In conclusion, EXTRA focuses on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new reconfigurable architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a design concept, and applications that are tuned to maximally exploit run-time reconfiguration techniques. Our goal is to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfigurable computing.

Deliverables

List of deliverables.
Initial demonstrators	Demonstrators, pilots, prototypes	2019-09-04 15:17:12
Project Handbook, e-mail reflector, web site and FTP site	Websites, patent fillings, videos etc.	2019-09-04 15:17:12
Integration and final demonstrators	Demonstrators, pilots, prototypes	2019-09-04 15:17:12

Take a look to the deliverables list in detail: detailed list of EXTRA deliverables.

Publications

List of publications.
year	authors and title	journal	last update
2016	Kit Cheung, Simon R. Schultz, Wayne Luk NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors published pages: , ISSN: 1662-453X, DOI: 10.3389/fnins.2015.00516	Frontiers in Neuroscience 9	2019-09-04
2017	A. Kulkarni, A. Werner, F. Fricke, D. Stroobandt and M. Huebner Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications published pages: , ISSN: , DOI:	3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017)	2019-09-04
2017	James Arram, Thomas Kaplan, Wayne Luk, Peiyong Jiang Leveraging FPGAs for Accelerating Short Read Alignment published pages: 1-1, ISSN: 1545-5963, DOI: 10.1109/TCBB.2016.2535385	IEEE/ACM Transactions on Computational Biology and Bioinformatics	2019-09-04
2017	M. Rabozzi, G. Natale, E. Del Sozzo, A. Scolari, L. Stornaiuolo, and M. D. Santambrogio Heterogeneous exascale supercomputing: the role of CAD in the exaFPGA project published pages: , ISSN: , DOI:	2017 Design, Automation Test in Europe Conference Exhibition (DATE)	2019-09-04
2016	M. Arnaboldi, M. Ferroni, M. D. Santambrogio Towards a Performance-Aware Power Capping Orchestrator for the Xen Hypervisor published pages: , ISSN: , DOI:	Embed With Linux (EWiLi) Workshop 2016	2019-09-04
2017	Eddie Hung, Tim Todman, Wayne Luk Transparent In-Circuit Assertions for FPGAs published pages: 1-1, ISSN: 0278-0070, DOI: 10.1109/TCAD.2016.2618862	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	2019-09-04
2016	Amit Kulkarni, Dirk Stroobandt MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization published pages: 341-359, ISSN: 0929-5585, DOI: 10.1007/s10617-016-9180-6	Design Automation for Embedded Systems 20/4	2019-09-04
2016	JoÃ£o M. P. Cardoso, JosÃ© G. F. Coutinho, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Fernando GonÃ§alves Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach published pages: 251-287, ISSN: 0038-0644, DOI: 10.1002/spe.2301	Software: Practice and Experience 46/2	2019-09-04
2016	Riccardo Cattaneo, Giuseppe Natale, Carlo Sicignano, Donatella Sciuto, Marco Domenico Santambrogio On How to Accelerate Iterative Stencil Loops published pages: 1-26, ISSN: 1544-3566, DOI: 10.1145/2842615	ACM Transactions on Architecture and Code Optimization 12/4	2019-09-04
2017	Gordon Inggs, David B. Thomas, Wayne Luk A Domain Specific Approach to High Performance Heterogeneous Computing published pages: 2-15, ISSN: 1045-9219, DOI: 10.1109/TPDS.2016.2563427	IEEE Transactions on Parallel and Distributed Systems 28/1	2019-09-04
2017	Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation published pages: 151-164, ISSN: 1063-8210, DOI: 10.1109/TVLSI.2016.2562361	IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25/1	2019-09-04
2017	L. Gan, H. Fu, O. Mencer, W. Luk, G. Yang Chapter Four - Data Flow Computing in Geoscience Applications published pages: 125-158, ISSN: , DOI: 10.1016/bs.adcom.2016.09.005		2019-09-04
2017	Giulio Stramondo, Ana Lucia Varbanescu and Catalin Bogdan Ciobanu How effective are custom parallel memories published pages: , ISSN: , DOI:	ICT.Open	2019-09-04
2017	Anna Maria Nestorov, Enrico Reggiani, Marco Domenico Santambrogio, Pavel Burovskiy, Hristina Palikareva and Tobias Becker A Scalable Dataflow Implementation of Curranâ€™s Approximation Algorithm published pages: , ISSN: , DOI:	Reconfigurable Architectures Workshop	2019-09-04
2016	Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip Leong, Yu Peng A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification published pages: 105-116, ISSN: , DOI: 10.1007/978-3-319-30481-6_9	Part of the Lecture Notes in Computer Science book series (LNCS, volume 9625)	2019-09-04
2016	Giulio Stramondo, Catalin Ciobanu, Ana Lucia Varbanescu The Case for Custom Parallel Memories: an Application-centric Analysis published pages: , ISSN: , DOI:		2019-09-04
2016	Amit Kulkarni, Dirk Stroobandt How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization published pages: 1-12, ISSN: 1687-7195, DOI: 10.1155/2016/5340318	International Journal of Reconfigurable Computing 2016	2019-09-04
2017	â€¢ Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev From exaflop to exaflow published pages: , ISSN: , DOI:	Proceedings of the Design Automation and Test in Europe Conference	2019-09-04
2017	George Charitopoulos, Charalampos Vatsolakis, Stefanos Sidiropoulos, Grigorios Chrysos and Dionisios Pnevmatikatos A Decoupled Access-Execute Architecture for Reconfigurable Accelerators published pages: , ISSN: , DOI:	11th HiPEAC Workshop on Reconfigurable Computing (WRC\'2017)	2019-09-04
2018	Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt Hierarchical force-based block spreading for analytical FPGA placement published pages: , ISSN: , DOI:	FPL 2018	2019-09-04
2018	Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu and Cees De Laat Towards Application-Centric Parallel Memories published pages: , ISSN: , DOI:	EuroPar Workshops 2018 -- HeteroPar\'18	2019-09-04
2018	Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies published pages: 39-52, ISSN: 1939-8018, DOI: 10.1007/s11265-017-1244-8	Journal of Signal Processing Systems 90/1	2019-09-04
2018	R. Zhao, H.C. Ng, W. Luk and X. Niu Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA published pages: , ISSN: , DOI:	International Conference on Field-Programmable Logic and Applications	2019-09-04
2018	Florian Fricke, AndrÃ© Werner, Keyvan Shahin, Michael Huebner CGRA Tool Flow for Fast Run-Time Reconfiguration published pages: 661-672, ISSN: , DOI: 10.1007/978-3-319-78890-6_53	Proc. of the 14th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)	2019-09-04
2018	Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei FP-BNN: Binarized neural network on FPGA published pages: 1072-1086, ISSN: 0925-2312, DOI: 10.1016/j.neucom.2017.09.046	Neurocomputing 275	2019-09-04
2017	Alexandra Kourfali, David Merodio Codinachs and Dirk Stroobandt Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs published pages: , ISSN: , DOI:	IEEE Conference on Radiation Effects on Components and Systems (RADECS)	2019-09-04
2018	Catalin Bogdan Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu, Andreas Brokalakis, Antonis Nikitakis, Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio, Grigorios Chrysos, Charalampos Vatsolakis, Charitopoulos Georgios, Dionisios Pnevmatikatos EXTRA: An Open Platform for Reconfigurable Architectures published pages: , ISSN: , DOI: 10.1145/3229631.3236092	Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVIII), 2018 International Conference on	2019-09-04
2017	Bridgette Cooper, Stephen Girdlestone, Pavel Burovskiy, Georgi Gaydadjiev, Vitali Averbukh, Peter J. Knowles, Wayne Luk Quantum Chemistry in Dataflow: Density-Fitting MP2 published pages: 5265-5272, ISSN: 1549-9618, DOI: 10.1021/acs.jctc.7b00649	Journal of Chemical Theory and Computation 13/11	2019-09-04
2018	A.-I. Cross, L. Guo, W. Luk and M. Salmon CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems, published pages: , ISSN: , DOI:	International Conference on Field-Programmable Logic and Applications	2019-09-04
2017	Alexandra Kourfali and Dirk Stroobandt In-Circuit FPGA Debugging using Parameterised Reconfigurations published pages: , ISSN: , DOI:	54th ACM/ESDA/IEEE Design Automation Conference (DAC)	2019-09-04
2018	Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance published pages: 629-642, ISSN: 0278-0070, DOI: 10.1109/TCAD.2017.2717786	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37/3	2019-09-04
2018	Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos and Dionisios N. Pnevmatikatos Accelerated Inference of Positive Selection on Whole Genomes published pages: , ISSN: , DOI:	International Conference on Field-Programmable Logic and Applications	2019-09-04
2018	Poona Bahrebar, Dirk Stroobandt Abacus turn model-based routing for NoC interconnects with switch or link failures published pages: 69-91, ISSN: 0141-9331, DOI: 10.1016/j.micpro.2018.01.005	Microprocessors and Microsystems 59	2019-09-04
2018	Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu HLS Support for Polymorphic Parallel Memories published pages: , ISSN: , DOI:	proceeding of the 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)	2019-09-04

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