Explore the words cloud of the PRIME project. It provides you a very rough idea of what is the project "PRIME" about.
The following table provides information about the project.
Coordinator |
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Organization address contact info |
Coordinator Country | Belgium [BE] |
Project website | http://www.prime-h2020.eu |
Total cost | 38˙296˙264 € |
EC max contribution | 12˙038˙776 € (31%) |
Programme |
1. H2020-EU.2.1.1.7. (ECSEL) |
Code Call | H2020-ECSEL-2015-1-RIA-two-stage |
Funding Scheme | ECSEL-RIA |
Starting year | 2015 |
Duration (year-month-day) | from 2015-12-01 to 2019-09-30 |
Take a look of project's partnership.
The goal of the PRIME project is to establish an open Ultra Low Power (ULP) Technology Platform containing all necessary design and architecture blocks and components which could enable the European industry to increase and strengthen their competitive and leading eco-system and benefit from market opportunities created by the Internet of Things (IoT) revolution. Over 3 years the project will develop and demonstrate the key building blocks of IoT ULP systems driven by the applications in the medical, agricultural, domestics and security domains. This will include development of high performance, energy efficient and cost effective technology platform, flexible design ecosystem (including IP and design flow), changes in architectural and power management to reduced energy consumption, security blocks based on PUF and finally the System of Chip and System in Package memory banks and processing implementations for IoT sensor node systems. Developped advanced as 22nm FDSOI low power technologies with logic, analog, RF and embedded new memory components (STT RAM and RRAM) together with innovative design and system architecture solutions will be used to build macros and demonstrate functionality and power reduction advantage of the new IoT device components. The PRIME project will realize several demonstrators of IoT system building blocks to show the proposed low power wireless solutions, functionality and performance of delivered design and technology blocks. The consortium semiconductor ecosystem (IDMs, design houses, R&D, tools & wafer suppliers, foundries, system/product providers) covers complementarily all desired areas of expertise to achieve the project goals. The project will enable an increase in Europe’s innovation capability in the area of ULP Technology, design and applications, creation of a competitive European eco-system and help to identify market leadership opportunities in security, mobility, healthcare and smart cost competitive manufacturing.
Public communication of final result | Other | 2020-02-12 17:41:42 |
Web page | Other | 2019-09-10 08:57:16 |
Take a look to the deliverables list in detail: detailed list of PRIME deliverables.
year | authors and title | journal | last update |
---|---|---|---|
2017 |
Kalishetthyhalli Mahadevaiah, Mamathamba PVD and ALD process development of advanced oxide-based RRAM-stacks published pages: , ISSN: , DOI: |
2019-12-17 | |
2020 |
Elbert Bechthum, Johan Dijkhuis, Ming Ding, Yuming He, Johan van den Heuvel, Paul Mateman, Gert-Jan van Schaik, Kenichi Shibata*, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Nick Winkel, Yao-Hong Li, Christian Bachmann A low-power BLE transceiver with support for phase-based ranging, featuring 5μs PLL locking time and 5.3ms ranging time, enabled by staircase-chirp PLL with sticky-lock channel-switching published pages: , ISSN: , DOI: |
2020 International Solid-State Circuits Conference | 2019-12-17 |
2019 |
Mattis Hasler, Robert Wittig, Emil Matus, Gerhard Fettweis Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion published pages: 1-10, ISSN: 1549-8328, DOI: 10.1109/tcsi.2019.2926134 |
IEEE Transactions on Circuits and Systems I: Regular Papers Print ISSN: 1549-8328 Electroni | 2019-12-17 |
2019 |
W. Schwarzenbach, B.-Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Maleville Advanced FD-SOI and Beyond Low Temperature SmartCutâ„¢ Enables High Density 3-D SoC Applications published pages: 863-868, ISSN: 2168-6734, DOI: 10.1109/jeds.2019.2916460 |
IEEE Journal of the Electron Devices Society 7 | 2019-12-17 |
2019 |
Hua Lv, João Fidalgo, Diana C. Leitão, Ana V. Silva, Thomas Kämpfe, Stefan Riedel, Juergen Langer, Jerzy Wrona, Berthold Ocker, Paulo P. Freitas, Susana Cardoso The annealing effect on memory state stability and interlayer coupling in perpendicular magnetic tunnel junctions with ultrathin MgO barrier published pages: 142-146, ISSN: 0304-8853, DOI: 10.1016/j.jmmm.2019.01.050 |
Journal of Magnetism and Magnetic Materials 477 | 2019-12-17 |
2019 |
M Hasler, R Wittig, E Matus, G Fettweis A Hybrid Execution Approach to Improve the Performance of Dataflow Applications published pages: , ISSN: , DOI: |
16th International SoC Design Conference | 2019-12-17 |
2019 |
Maciej Haras, Michał Markiewicz, Stéphane Monfray, Thomas Skotnicki Pulse mode of operation – A new booster of TEG, improving power up to X2.7 – to better fit IoT requirements published pages: 104204, ISSN: 2211-2855, DOI: 10.1016/j.nanoen.2019.104204 |
Nano Energy In Press | 2019-12-17 |
2019 |
S Nam, E Matus, G Fettweis Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs published pages: , ISSN: , DOI: |
32th IEEE International System-On-Chip Conference | 2019-12-17 |
2017 |
S Haas, G Fettweis Energy-Efficient Hash Join Implementations in Hardware-Accelerated MPSoCs published pages: , ISSN: , DOI: |
Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures Eighth International Workshop o | 2019-12-17 |
2018 |
Hua Lv, Diana C. Leitao, Zhiwei Hou, Paulo P. Freitas, Susana Cardoso, Thomas Kämpfe, Johannes Müller, Juergen Langer, Jerzy Wrona Barrier breakdown mechanism in nano-scale perpendicular magnetic tunnel junctions with ultrathin MgO barrier published pages: 55908, ISSN: 2158-3226, DOI: 10.1063/1.5007656 |
AIP Advances 8/5 | 2019-09-10 |
2017 |
Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig MESH: Explicit and Flexible Generation of Analog Arrays published pages: , ISSN: , DOI: |
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) annually | 2019-09-10 |
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The information about "PRIME" are provided by the European Opendata Portal: CORDIS opendata.