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MEEP SIGNED

The MareNostrum Experimental Exascale Platform

Total Cost €

EC-Contrib. €

Partnership

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MEEP project word cloud

Explore the words cloud of the MEEP project. It provides you a very rough idea of what is the project "MEEP" about.

porting provides accelerator cpu functional functions foundation ip fpga purposes fpgas profiler maturity ways emulation hpc drivers debugger saving base follow risc extend supercomputer platform designs interfaces silicon tested core chips supercomputers source architecture host flexible memory validated meep academic toolchain compiler limitations hardware connectivity explore os co money exascale rapid standard ecosystem tools experimental pop2 series marenostrum library moving cores infrastructure shell accelerating speed ips improvements deploy demonstrating validating ideas map enhanced experimentation epi readiness building simulation accelerators evaluation time software leverage prototyping coe

Project "MEEP" data sheet

The following table provides information about the project.

Coordinator	BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION Organization address address: Calle Jordi Girona 31 city: BARCELONA postcode: 8034 website: www.bsc.es contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.
Coordinator Country	Spain [ES]
Total cost	10˙378˙125 €
EC max contribution	5˙150˙000 € (50%)
Programme	1. H2020-EU.2.1.1.2. (Next generation computing: Advanced and secure computing systems and technologies, including cloud computing)
Code Call	H2020-JTI-EuroHPC-2019-3
Funding Scheme	RIA
Starting year	2020
Duration (year-month-day)	from 2020-01-01 to 2022-12-31

Partnership

Take a look of project's partnership.

#	participants	country	role	EC contrib. [€]
1	BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION Organization address address: Calle Jordi Girona 31 city: BARCELONA postcode: 8034 website: www.bsc.es contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	ES (BARCELONA)	coordinator	4˙881˙250.00
2	SVEUCILISTE U ZAGREBU FAKULTET ELEKTROTEHNIKE I RACUNARSTVA SVEUCILISTE U ZAGREBU FAKULTET ELEKTROTEHNIKE I RACUNARSTVA Organization address address: UNSKA 3 city: ZAGREB postcode: 10000 website: www.fer.hr contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	HR (ZAGREB)	participant	140˙000.00
3	TURKIYE BILIMSEL VE TEKNOLOJIK ARASTIRMA KURUMU TURKIYE BILIMSEL VE TEKNOLOJIK ARASTIRMA KURUMU Organization address address: Ataturk Bulvari 221 city: ANKARA postcode: 6100 website: www.tubitak.gov.tr contact info title: n.a. name: n.a. surname: n.a. function: n.a. email: n.a. telephone: n.a. fax: n.a.	TR (ANKARA)	participant	128˙750.00

Map

Project objective

The MareNostrum Experimental Exascale Platform (MEEP) is a flexible FPGA-based emulation platform that will explore hardware/software co-designs for Exascale Supercomputers and other hardware targets, based on European-developed IP. MEEP provides two very important functions: 1) An evaluation platform of pre-silicon IP and ideas, at speed and scale and 2) A software development and experimentation platform to enable software readiness for new hardware. MEEP enables software development, accelerating software maturity, compared to the limitations of software simulation. IP can be tested and validated before moving to silicon, saving time and money. The objectives of MEEP are to leverage and extend projects like EPI and the POP2 CoE in the following ways: â— Define, develop, and deploy an FPGA-based emulation platform targeting European-based Exascale Supercomputer RISC-V-based IP development, especially hardware/software co-design. â— Develop a base FPGA shell that provides memory and I/O connectivity to the host CPU and other FPGAs. â— Build FPGA tools and support to map enhanced EPI and MEEP IP into the FPGA core, validating and demonstrating European IP. â— Develop the software toolchain (compiler, debugger, profiler, OS, and drivers) for RISC-V based accelerators to enable application development and porting. MEEP will deliver a series of Open-Source IPs, when possible, that can be used for academic purposes and integrated into a functional accelerator or cores for traditional and emerging HPC applications. This is an exciting target for IPs generated from projects like EPI, and an IP source for follow-on projects as well. MEEP will provide a foundation for building European-based chips and infrastructure to enable rapid prototyping using a library of IPs and a standard set of interfaces to the Host CPU and other FPGAs in the system using the FPGA shell. In addition to RISC-V architecture and hardware ecosystem improvements.

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The information about "MEEP" are provided by the European Opendata Portal: CORDIS opendata.