FASTCUDA
Open Source FPGA Accelerator & Hardware Software Codesign Toolset for CUDA Kernels
| Coordinatore | INGENIERIA DE SISTEMAS INTENSIVOS EN SOFTWARE
Organization address
address: VALDESANGIL 16 contact info |
| Nazionalità Coordinatore | Spain [ES] |
| Totale costo | 1˙603˙596 € |
| EC contributo | 1˙195˙755 € |
| Programma | FP7-SME
Specific Programme "Capacities": Research for the benefit of SMEs |
| Code Call | FP7-SME-2011 |
| Funding Scheme | BSG-SME |
| Anno di inizio | 2011 |
| Periodo (anno-mese-giorno) | 2011-11-01 - 2013-10-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
INGENIERIA DE SISTEMAS INTENSIVOS EN SOFTWARE
Organization address
address: VALDESANGIL 16 contact info |
ES (MADRID) | coordinator | 411˙100.00 |
| 2 |
FSRESULT GMBH
Organization address
address: BAADERSTRASSE 59 contact info |
DE (MUNCHEN) | participant | 386˙736.50 |
| 3 |
ARDORAN OU
Organization address
address: "HELTERMAA, PUHALEPA VALD" contact info |
EE (HIIUMAA) | participant | 378˙212.00 |
| 4 |
POLITECNICO DI TORINO
Organization address
address: Corso Duca degli Abruzzi 24 contact info |
IT (TORINO) | participant | 7˙724.00 |
| 5 |
UNIVERSIDAD POLITECNICA DE MADRID
Organization address
address: Calle Ramiro de Maeztu 7 contact info |
ES (MADRID) | participant | 6˙866.00 |
| 6 |
TELECOMMUNICATIONS SYSTEMS INSTITUTE.
Organization address
address: Technical University of Crete Campus - Kounoupidiana contact info |
EL (CHANIA) | participant | 5˙116.05 |
Mappa
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Obiettivo del progetto (Objective)
'Europe has a strong leadership in the domains of intelligent telecommunications, multimedia, and automotive systems. However, the exponential increase in complexity of intelligent systems threatens the European competitiveness. In order to solve today’s challenges of high-complex design for embedded electronic systems, a number of approaches have been tried. Hardware-software codesign is the first big step and an essential enabling technology towards this end. Electronic System Level (ESL) design methodologies is the next big step which addresses the complexity problem by elevating design to a higher level of abstraction, resulting in a more predictable and productive design process. Finally, parallel hardware platforms such as Graphical Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs) are becoming very popular within PC-based heterogeneous systems for speeding up numerous compute-intensive applications. FASTCUDA is a platform that provides the necessary software tools, hardware architecture, and design methodology to efficiently adapt CUDA (a parallel-computing architecture and API which is driven by the GPU industry, with wide adoption in many diverse fields ranging from molecular dynamics, to computational chemistry, to image or video processing, etc.) into a new FPGA design flow. With FASTCUDA, the CUDA kernels of a CUDA-based application are automatically partitioned into two groups: some are compiled and executed in parallel software, while the remaining are synthesized and implemented in hardware. A modern low power FPGA provides the processing power (via hundreds of embedded micro-CPUs) and the logic capacity for the implementation of all the software and the hardware components. In particular, we plan to join the numerous on-going efforts in industry and academia to create a unified best-practice, industrial-quality, open-source framework that will enable an easier transition from research results to industrial exploitation.'