Coordinatore | SECONDA UNIVERSITÀ DEGLI STUDI DI NAPOLI
Organization address
address: VIALE BENEDUCE 10 contact info |
Nazionalità Coordinatore | Italy [IT] |
Totale costo | 249˙600 € |
EC contributo | 187˙200 € |
Programma | FP7-JTI
Specific Programme "Cooperation": Joint Technology Initiatives |
Code Call | SP1-JTI-CS-2011-03 |
Funding Scheme | JTI-CS |
Anno di inizio | 2012 |
Periodo (anno-mese-giorno) | 2012-06-01 - 2014-12-31 |
# | ||||
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1 |
Nome Ente NON disponibile
Organization address
address: VIALE BENEDUCE 10 contact info |
IT (CASERTA) | coordinator | 74˙700.00 |
2 |
AEROMECHS SRL
Organization address
address: VIA PARENTE 10 contact info |
IT (AVERSA CE) | participant | 112˙500.00 |
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
'The main objective of the proposal is the development of an hardware device able to implement an innovative power management (I-LPM) function for an aeronautical electrical network. The proposal is based on the two keypoints. First one concerns the I-LPM strategy for the specific application, that will be first derived and tested in a simulation environment. In a second phase the above strategy will be implemented, adopting semi-automatic techniques for translation of the simulation model into firmware. Second keypoint is about an EPC (Electrical Power Center) hardware extension that will be designed and realized, where a modular approach will be considered for the overall equipment implementation. Each cell will be composed by a programmable device, an interfacing stage and possibly by an innovative power device switching component. A “master” module will be able to implement the I-LPM concept and communicate with “slave” modules for correct energy management strategy implementation. Different types of “slave” modules will be considered, taking into account the necessity of I-LPM strategy implementation for both “fixed power” and “variable power” loads. A preliminary analysis phase will be conducted in order to analyze the fundamental requirements for the project objectives and derive the specifications set. After the models validation, it will be necessary to implement the derived models as real electronic components. Before integration on the ETB (Electrical Test Bench), the hardware performances will be verified towards the expected results, considering the requirements derived in the first stage as well as the obtained simulation results. Next, a complete test case set will be performed in order to evidence the expected results fulfillment. Finally, an optimization stage will consider the user's feedbacks and appropriately manage potential faults occurring on the electrical network.'