Coordinatore | CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
Organization address
address: avenue des martyrs 25 contact info |
Nazionalità Coordinatore | France [FR] |
Totale costo | 4˙414˙901 € |
EC contributo | 3˙200˙000 € |
Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
Code Call | FP7-ICT-2011-8 |
Funding Scheme | CP |
Anno di inizio | 2012 |
Periodo (anno-mese-giorno) | 2012-10-01 - 2015-09-30 |
# | ||||
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1 |
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
Organization address
address: avenue des martyrs 25 contact info |
FR (Grenoble) | coordinator | 0.00 |
2 |
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Organization address
address: RUE LEBLANC 25 contact info |
FR (PARIS 15) | participant | 0.00 |
3 |
EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZURICH
Organization address
address: Raemistrasse 101 contact info |
CH (ZUERICH) | participant | 0.00 |
4 |
INSTITUT POLYTECHNIQUE DE GRENOBLE
Organization address
address: AVENUE FELIX VIALLET 46 contact info |
FR (GRENOBLE CEDEX 1) | participant | 0.00 |
5 |
Karlsruher Institut fuer Technologie
Organization address
address: Kaiserstrasse 12 contact info |
DE (Karlsruhe) | participant | 0.00 |
6 |
NATIONAL CENTER FOR SCIENTIFIC RESEARCH "DEMOKRITOS"
Organization address
address: Patriarchou Gregoriou Str. contact info |
EL (AGHIA PARASKEVI) | participant | 0.00 |
7 |
Singulus Technologies AG
Organization address
address: Hanauer Landstrasse 103 contact info |
DE (KAHL AM MAIN) | participant | 0.00 |
8 |
TOPLINK INNOVATION
Organization address
city: La Seyne sur Mer contact info |
FR (La Seyne sur Mer) | participant | 0.00 |
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The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption will soon start to limit microprocessor performance growth. The goal of the spOt project is to modify the memory hierarchy by the integration of non-volatility (NV) as a new feature of memory cache, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing.nTo accomplish this aggressive goal, limitations of present NV memories in terms of speed and endurance must be overcome and new architectures taking full benefit of these new functionalities must be developed. The consortium will base its research on a recent discovery achieved jointly by SPINTEC and ICN, called 'Spin Orbit Torque' (SOT). This disruptive technology, which can be viewed as the ultimate evolution of Spin Transfer Torque, offers the same non-volatility and compliance with technological nodes below 22nm, with the addition of lower power consumption, cache-compatible high speed, and truly infinite endurance.nTo demonstrate its viability for cache, a number of identified technology roadblocks are addressed by the spOt project through its 5 work-packages and 4 intermediate goals: i) the realization of a fast write, low power, high read signal single memory cell ii) the development of a single cell architecture (standard cell) with minimal footprint iii) A stand-alone memory test chip with full functionality iv) The full chip simulation of a low-power/normally-off multicore processor.nThe final objective of the project is twofold: The fabrication of a SOT memory test chip, which would be benchmarked against existing and forecasted solutions in order to demonstrate the integrability and manufacturability of this new technology; The design and full chip simulation of a novel multicore processor integrating embedded SOT memory, in order to demonstrate the systemability of such approach.