TOLOP
Towards Low Power ICT
| Coordinatore | HITACHI EUROPE LIMITED
Organization address
address: Hitachi Cambridge Laboratory JJ Thompson Avenue Madingley Road contact info |
| Nazionalità Coordinatore | United Kingdom [UK] |
| Totale costo | 3˙320˙415 € |
| EC contributo | 1˙999˙311 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2011-8 |
| Funding Scheme | CP |
| Anno di inizio | 2012 |
| Periodo (anno-mese-giorno) | 2012-09-01 - 2015-08-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
HITACHI EUROPE LIMITED
Organization address
address: Hitachi Cambridge Laboratory JJ Thompson Avenue Madingley Road contact info |
UK (Cambridge) | coordinator | 0.00 |
| 2 |
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Organization address
address: RUE LEBLANC contact info |
FR (PARIS 15) | participant | 0.00 |
| 3 |
THE HEBREW UNIVERSITY OF JERUSALEM
Organization address
address: GIVAT RAM CAMPUS contact info |
IL (JERUSALEM) | participant | 0.00 |
| 4 |
UNIVERSITE DE LIEGE
Organization address
city: LIEGE contact info |
BE (LIEGE) | participant | 0.00 |
| 5 |
UNIVERSITY OF NEW SOUTH WALES
Organization address
address: ANZAC PARADE contact info |
AU (SYDNEY) | participant | 0.00 |
| 6 |
UPPSALA UNIVERSITET
Organization address
address: St Olofsgatan contact info |
SE (UPPSALA) | participant | 0.00 |
Mappa
Word cloud
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Obiettivo del progetto (Objective)
TOLOP comprises investigations into three of the levels necessary for a paradigm shift in low-power electronics:n1. Fabrication and measurement of devices which are inherently low-power in switching operation at room temperaturen2 . Theory of specific device implementations for each of those technologies to explain and validate the principles behind their low-power capabilities.n3. Design of architecture to enable the circuit operation of these technologies for overall low-power circuit operation.nThere will be an investigation of the inherent losses at realistic switching rates, and estimations of the device-circuit-operation trade-offs for minimising energy consumption. Metrics such as the energy-delay product will be provided for each implementation and benchmarked against existing commercial and research technologies.nThe consortium brings together leading European institutions in this field, and allows the overall optimisation of energy consumption in realistic conditions, including device fabrication, device operation and circuit operation at several levels.nTarget outcomes:n1. Novel single-atom, single-electron and spintronic devices will be investigated experimentally. In the first two cases, the structures are inherently CMOS-compatible whilst in the third a higher-risk approach will be taken whilst still addressing manufacturabilityn2. Both non-Boolean implementations such as multi-valued logic and parallel logic, and optimised Boolean logic implementations will be addressed. Non Boolean logic has the potential for exponential improvement in power needs.n3. Architectures and operating protocols will be designed to optimise the total power consumption of a circuit-level implementation, taking into account measured and estimated losses at realistic operating rates and temperaturesnnDevice-level proof of concept will be achieved experimentally, driving the design of specific implementations, with theoretical investigation of viability in a realistic circuit