TOLOP

Towards Low Power ICT

 Coordinatore HITACHI EUROPE LIMITED 

 Organization address address: Hitachi Cambridge Laboratory JJ Thompson Avenue Madingley Road
city: Cambridge
postcode: CB3 0HE

contact info
Titolo: Dr.
Nome: David
Cognome: Williams
Email: send email
Telefono: +44 1223 442902
Fax: +44 1223 467942

 Nazionalità Coordinatore United Kingdom [UK]
 Totale costo 3˙320˙415 €
 EC contributo 1˙999˙311 €
 Programma FP7-ICT
Specific Programme "Cooperation": Information and communication technologies
 Code Call FP7-ICT-2011-8
 Funding Scheme CP
 Anno di inizio 2012
 Periodo (anno-mese-giorno) 2012-09-01   -   2015-08-31

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    HITACHI EUROPE LIMITED

 Organization address address: Hitachi Cambridge Laboratory JJ Thompson Avenue Madingley Road
city: Cambridge
postcode: CB3 0HE

contact info
Titolo: Dr.
Nome: David
Cognome: Williams
Email: send email
Telefono: +44 1223 442902
Fax: +44 1223 467942

UK (Cambridge) coordinator 0.00
2    COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

 Organization address address: RUE LEBLANC
city: PARIS 15
postcode: 75015

contact info
Titolo: Dr.
Nome: marc
Cognome: sanquer
Email: send email
Telefono: +33 4 38 78 43 67
Fax: +33 4 38 78 50 96

FR (PARIS 15) participant 0.00
3    THE HEBREW UNIVERSITY OF JERUSALEM

 Organization address address: GIVAT RAM CAMPUS
city: JERUSALEM
postcode: 91904

contact info
Titolo: Ms.
Nome: Jane
Cognome: Turner
Email: send email
Telefono: +972 2 6586676
Fax: +972 72 2447007

IL (JERUSALEM) participant 0.00
4    UNIVERSITE DE LIEGE

 Organization address city: LIEGE
postcode: 4000

contact info
Titolo: Dr.
Nome: Isabelle
Cognome: Halleux
Email: send email
Telefono: +32 4 3665428
Fax: +32 4 3665558

BE (LIEGE) participant 0.00
5    UNIVERSITY OF NEW SOUTH WALES

 Organization address address: ANZAC PARADE
city: SYDNEY
postcode: 2052

contact info
Titolo: Mrs.
Nome: Susanne
Cognome: Clark
Email: send email
Telefono: +61 2 9385 6989
Fax: +61 2 9385 7238

AU (SYDNEY) participant 0.00
6    UPPSALA UNIVERSITET

 Organization address address: St Olofsgatan
city: UPPSALA
postcode: 751 05

contact info
Titolo: Mr.
Nome: Patrik
Cognome: Armuand
Email: send email
Telefono: 46184715701
Fax: 4618511925

SE (UPPSALA) participant 0.00

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

implementations    technologies    power    consumption    fabrication    whilst    rates    levels    logic    investigation    energy    operation    switching    losses    experimentally    realistic    inherently    circuit    device    boolean       single   

 Obiettivo del progetto (Objective)

TOLOP comprises investigations into three of the levels necessary for a paradigm shift in low-power electronics:n1. Fabrication and measurement of devices which are inherently low-power in switching operation at room temperaturen2 . Theory of specific device implementations for each of those technologies to explain and validate the principles behind their low-power capabilities.n3. Design of architecture to enable the circuit operation of these technologies for overall low-power circuit operation.nThere will be an investigation of the inherent losses at realistic switching rates, and estimations of the device-circuit-operation trade-offs for minimising energy consumption. Metrics such as the energy-delay product will be provided for each implementation and benchmarked against existing commercial and research technologies.nThe consortium brings together leading European institutions in this field, and allows the overall optimisation of energy consumption in realistic conditions, including device fabrication, device operation and circuit operation at several levels.nTarget outcomes:n1. Novel single-atom, single-electron and spintronic devices will be investigated experimentally. In the first two cases, the structures are inherently CMOS-compatible whilst in the third a higher-risk approach will be taken whilst still addressing manufacturabilityn2. Both non-Boolean implementations such as multi-valued logic and parallel logic, and optimised Boolean logic implementations will be addressed. Non Boolean logic has the potential for exponential improvement in power needs.n3. Architectures and operating protocols will be designed to optimise the total power consumption of a circuit-level implementation, taking into account measured and estimated losses at realistic operating rates and temperaturesnnDevice-level proof of concept will be achieved experimentally, driving the design of specific implementations, with theoretical investigation of viability in a realistic circuit

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