TIPS

Technology development and fabrication of Integrated solid-state Power Switches

 Coordinatore PRIMES 

 Organization address address: 67 BOULEVARD PIERRE RENAUDET
city: TARBES
postcode: 65000

contact info
Titolo: Ms.
Nome: Estelle
Cognome: Grall
Email: send email
Telefono: 330563000000
Fax: +0033 0562968293

 Nazionalità Coordinatore France [FR]
 Totale costo 534˙840 €
 EC contributo 401˙130 €
 Programma FP7-JTI
Specific Programme "Cooperation": Joint Technology Initiatives
 Code Call SP1-JTI-CS-2013-02
 Funding Scheme JTI-CS
 Anno di inizio 2015
 Periodo (anno-mese-giorno) 2015-02-01   -   2016-05-31

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    PRIMES

 Organization address address: 67 BOULEVARD PIERRE RENAUDET
city: TARBES
postcode: 65000

contact info
Titolo: Ms.
Nome: Estelle
Cognome: Grall
Email: send email
Telefono: 330563000000
Fax: +0033 0562968293

FR (TARBES) coordinator 401˙130.00

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

cooling    sided    double    structure    modules    technological    created    platform    semiconductor    bumps    power    international    primes    components   

 Obiettivo del progetto (Objective)

'PRIMES has been created as a legal and independant entity, inheriting the successful experience of PEARL Laboratory. This has allowed to give to the structure a wide and strong international visibility as one of the best European technological platform specialized in power integration. PRIMES puts a huge effort in developing virtual model solutions for power electronics components and systems, combined to a prototyping and characterization platform to be able to design, simulate, manufacture and characterize new power module technological demonstrators at the same place. PRIMES bondwire-less technology with double-sided semiconductor cooling has been demonstrated for high power devices. Such technology is centered on the use of bumps for connecting the surface side of vertical power components and enables a significant improvement in power density as compared with standard IGBT modules. Chips interconnection is ensured by flat substrates both on the bottom and on the top side; additional bumps are inserted on the sides of the structure to enhance mechanical stiffness and reduce stress at device level; after proper insulation, the structure is apt for double-sided cooling, with improved performance of the semiconductor devices. The results of the project will be produced under license by the aPSI3D start-up, created in order to have a European manufacturer abble to produce specific integrated power modules. The results will be protected by patents or spreadly disseminated through international conferencies and publications.'

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