TIPS
Thin Interconnected Package Stacks
| Coordinatore |
Organization address
address: Phase 2 Castlegate Business ParkPortskewett contact info |
| Nazionalità Coordinatore | Non specificata |
| Totale costo | 42 € |
| EC contributo | 0 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Anno di inizio | 2008 |
| Periodo (anno-mese-giorno) | 2008-09-08 - 2012-03-07 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
MICROSEMI SEMICONDUCTOR LIMITED
Organization address
address: Phase 2 Castlegate Business ParkPortskewett contact info |
UK (Newport) | coordinator | 0.00 |
| 2 |
HIGHTEC MC AG
Organization address
address: FABRIKSTRASSE contact info |
CH (LENZBURG) | participant | 0.00 |
| 3 |
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Organization address
address: Kapeldreef contact info |
BE (LEUVEN) | participant | 0.00 |
| 4 |
OTICON A/S
Organization address
address: KONGEBAKKEN 9 contact info |
DK (SMORUM) | participant | 0.00 |
| 5 |
TECHNISCHE UNIVERSITAT BERLIN
Organization address
address: Strasse des 17 Juni contact info |
DE (BERLIN) | participant | 0.00 |
| 6 |
WUERTH ELEKTRONIK ROT AM SEE GMBH & CO. KG
Organization address
address: RUDOLF-DIESEL-STRASSE 10 contact info |
DE (ROT AM SEE) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
The project TIPS aims at the conflation of embedding technologies for electronic components into extremely thin packages and the interconnection of those packages into stacked electronic systems. The testing of individual packages before stacking is performed will mitigate stacked package yield issues.nEmbedding of components will be developed starting from a basis of different technical approaches, depending on component type (active or passive), dimension and commercial availability. In order to reach the targeted stacked package thickness of 100 µm at maximum, the thickness of the embedded electrical components will be sub 50 µm.nIn this way modular thin packages will be realized, containing either arrays of or single electronic components. All packages have in common the same interface interconnection scheme to the next package. The interconnection scheme is to be developed in the project. The top and bottom package will have a layout for assembly of SMD components on the one hand or a ball grid array for soldering of the package stack onto a substrate board. Whether the packages stacks are interconnected within the stacking process or after stacking will be defined in the project. It is crucial to the outcome of the project that the stacking/interconnection is a highly robust process with an extremely low reject rate. Furthermore the realized package stacks have to withstand subsequent harsh process steps such as reflow soldering. Therefore early and continuous reliability testing of the packages as well as of packages stacks will be preformed.nViability and cost effectiveness of the developed technologies will be addressed throughout the development. In this way a future application of the technology will be more likely. Demonstrators for medical applications will be realized, where miniaturization and high functionality are the primary objectives.