PREDICTMP
Predictive Techniques for System Level Analysis of Multi-Processors
| Coordinatore | BOGAZICI UNIVERSITESI
Organization address
address: BEBEK contact info |
| Nazionalità Coordinatore | Turkey [TR] |
| Totale costo | 100˙000 € |
| EC contributo | 100˙000 € |
| Programma | FP7-PEOPLE
Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013) |
| Code Call | FP7-PEOPLE-2007-4-3-IRG |
| Funding Scheme | MC-IRG |
| Anno di inizio | 2009 |
| Periodo (anno-mese-giorno) | 2009-02-02 - 2013-02-01 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
BOGAZICI UNIVERSITESI
Organization address
address: BEBEK contact info |
TR (ISTANBUL) | coordinator | 0.00 |
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Obiettivo del progetto (Objective)
'Emerging multi-processor products, such as Multi-Processor System on Chips (MPSoC), exploit concurrency to spread work around a system improving performance. European competitiveness in microelectronics such as wireless, networking, telecommunications, automobile, and consumer products relies heavily on improving reliability of such multi-processor systems. Electronic System Level (ESL) design methods and tools are important abstraction techniques to reduce complexity introduced due to concurrency; however, system level tools are still at their infancy. At the same time, traditional simulation based verification approaches fail to preserve concurrency that is inherent in such systems and suffer from the pitfalls of ad hoc specification. Similarly, formal verification is limited in its capacity and application domain. In this project, we will develop system level analysis techniques to increase reliability of concurrent multi-processor systems. In particular, we propose to develop novel system level predictive runtime verification techniques that preserve concurrency information and exploit it to find both actual and potential errors from executions of system level models. At the same time, we will develop system level error diagnosis techniques and coverage metrics to ultimately reduce verification and debugging time. New research and tools will be developed with a focus on automation and scalability and experiments will be performed on industrial applications.'