ADAGIO
ADAptive circuit techniques for current-mode ultra low-power diGItal Integrated Circuits
| Coordinatore | UNIVERSITA' DEGLI STUDI DI SIENA
Organization address
address: VIA BANCHI DI SOTTO 55 contact info |
| Nazionalità Coordinatore | Italy [IT] |
| Totale costo | 127˙120 € |
| EC contributo | 127˙120 € |
| Programma | FP7-PEOPLE
Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013) |
| Code Call | FP7-PEOPLE-IOF-2008 |
| Funding Scheme | MC-IOF |
| Anno di inizio | 2009 |
| Periodo (anno-mese-giorno) | 2009-05-10 - 2011-05-09 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
UNIVERSITA' DEGLI STUDI DI SIENA
Organization address
address: VIA BANCHI DI SOTTO 55 contact info |
IT (SIENA) | coordinator | 127˙120.31 |
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Obiettivo del progetto (Objective)
'In the last years, the demand for ultra-low power integrated circuits with sub-1mW power consumption has been rapidly growing, due to the diffusion of applications relying on a large number of circuit nodes that are powered with tiny batteries or extract their energy from the environment (e.g., wireless sensor networks). These circuits must also be provided with sufficient computing capability for signal processing purposes, hence the design of ultra-low power digital circuits is a key aspect in this area. In this project, innovative circuit techniques to design ultra-low power digital circuits are developed. The MOS Current-Mode Logic (MCML) logic style is adopted in place of the standard sub-threshold CMOS logic, as MCML circuits were recently shown to be very well suited for ultra-low power operation thanks to the good control of their bias current. In addition, the prospective research activity targets the development of an efficient tuning scheme that adaptively varies the MCML gate bias current to compensate the inevitably large delay variations, adapt the power consumption to the available energy and the required performance, as well as to suppress the power contribution of inactive blocks. Accordingly, criteria and methods to design MCML standard cell libraries and use them in standard CAD design flows will be developed. To further reduce the consumption, an ultra-low voltage technique to halve the minimum supply voltage of MCML circuits will be introduced. Compared to sub-threshold standard CMOS logic, the joint adoption of the MCML logic style and the adaptive scheme is expected to significantly reduce the power consumption and to strongly enhance the circuit robustness against variations. Besides, the ability to tune the power consumption and the performance allows for using the same digital core for multiple applications, which is the premise to the design and the reuse of ultra-low power Intellectual Properties with assigned power specifications.'