2PARMA
PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures
| Coordinatore | POLITECNICO DI MILANO
Organization address
address: via Ponzio 34/5 contact info |
| Nazionalità Coordinatore | Italy [IT] |
| Totale costo | 3˙883˙704 € |
| EC contributo | 2˙741˙000 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-4 |
| Funding Scheme | CP |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-01-01 - 2013-03-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
POLITECNICO DI MILANO
Organization address
address: via Ponzio 34/5 contact info |
IT (Milano) | coordinator | 0.00 |
| 2 |
FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V
Organization address
address: Hansastrasse contact info |
DE (MUNCHEN) | participant | 0.00 |
| 3 |
INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS
Organization address
address: Patission Str. contact info |
EL (ATHINA) | participant | 0.00 |
| 4 |
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Organization address
address: Kapeldreef contact info |
BE (LEUVEN) | participant | 0.00 |
| 5 |
RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHEN
Organization address
address: Templergraben contact info |
DE (AACHEN) | participant | 0.00 |
| 6 |
STMICROELECTRONICS GRENOBLE 2 SAS
Organization address
address: RUE JULES HOROWITZ contact info |
FR (GRENOBLE) | participant | 0.00 |
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Obiettivo del progetto (Objective)
The current trend in computing architectures is to replace complex superscalar architectures with small homogeneous processing units connected by an on-chip network. This trend is mostly dictated by inherent silicon technology frontiers, which are getting as closer as the process densities levels increase. The number of cores to be integrated in a single chip is expected to rapidly increase in the coming years, moving from multi-core to many-core architectures. This trend will require a global rethinking of software and hardware design approaches.nThis class of computing systems (Many-core Computing Fabric) promises to increase performance, scalability and flexibility if appropriate design and programming methodologies will be defined to exploit the high degree of parallelism exposed by the architecture. Other potential benefits of Many-core Computing Fabric include energy efficiency, improved silicon yield, and accounting for local process variations. To exploit these potential benefits, effective run-time power and resource management techniques are needed. With respect to conventional computing architectures, Many-core Computing Fabric offers some customisation capabilities to extend and/or configure at run-time the architectural template to address a variable workload.nThe 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures. To this purpose, a proper Consortium has been set up to gather the required expertise in the areas of system/application software and computing architectures.The 2PARMA project focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable bytecode, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics.