2PARMA

PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures

Coordinatore	POLITECNICO DI MILANO    more  Organization address address: via Ponzio 34/5 city: Milano postcode: 20133 contact info Titolo: Prof. Nome: CRISTINA Cognome: SILVANO Email: send email Telefono: +39 02 23993692 Fax: +39 02 23993411
Nazionalità Coordinatore	Italy [IT]
Totale costo	3˙883˙704 €
EC contributo	2˙741˙000 €
Programma	FP7-ICT Specific Programme "Cooperation": Information and communication technologies
Code Call	FP7-ICT-2009-4
Funding Scheme	CP
Anno di inizio	2010
Periodo (anno-mese-giorno)	2010-01-01   -   2013-03-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	POLITECNICO DI MILANO  Organization address address: via Ponzio 34/5 city: Milano postcode: 20133 contact info Titolo: Prof. Nome: CRISTINA Cognome: SILVANO Email: send email Telefono: +39 02 23993692 Fax: +39 02 23993411	IT (Milano)	coordinator	0.00
2	FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V  Organization address address: Hansastrasse city: MUNCHEN postcode: 80686 contact info Titolo: Mr. Nome: Christoph Cognome: Schulte Email: send email Telefono: +49 8912052728 Fax: +49 8912057534	DE (MUNCHEN)	participant	0.00
3	INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS  Organization address address: Patission Str. city: ATHINA postcode: 10682 contact info Titolo: Prof. Nome: Yannis Cognome: Vassiliou Email: send email Telefono: +30 210 7724374 Fax: +30 210 7722456	EL (ATHINA)	participant	0.00
4	INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW  Organization address address: Kapeldreef city: LEUVEN postcode: 3001 contact info Titolo: Ms. Nome: Christine Cognome: VanHoutven Email: send email Telefono: +32 16281613 Fax: +32 16281812	BE (LEUVEN)	participant	0.00
5	RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHEN  Organization address address: Templergraben city: AACHEN postcode: 52062 contact info Titolo: Mr. Nome: Michael Cognome: Rieb Email: send email Telefono: +49 2418027622 Fax: +49 2418022195	DE (AACHEN)	participant	0.00
6	STMICROELECTRONICS GRENOBLE 2 SAS  Organization address address: RUE JULES HOROWITZ city: GRENOBLE postcode: 38000 contact info Titolo: Mr. Nome: Fabrice Cognome: Graignic Email: send email Telefono: +33 15 80 77 988 Fax: +33 15 80 77 916	FR (GRENOBLE)	participant	0.00

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 Obiettivo del progetto (Objective)

The current trend in computing architectures is to replace complex superscalar architectures with small homogeneous processing units connected by an on-chip network. This trend is mostly dictated by inherent silicon technology frontiers, which are getting as closer as the process densities levels increase. The number of cores to be integrated in a single chip is expected to rapidly increase in the coming years, moving from multi-core to many-core architectures. This trend will require a global rethinking of software and hardware design approaches.nThis class of computing systems (Many-core Computing Fabric) promises to increase performance, scalability and flexibility if appropriate design and programming methodologies will be defined to exploit the high degree of parallelism exposed by the architecture. Other potential benefits of Many-core Computing Fabric include energy efficiency, improved silicon yield, and accounting for local process variations. To exploit these potential benefits, effective run-time power and resource management techniques are needed. With respect to conventional computing architectures, Many-core Computing Fabric offers some customisation capabilities to extend and/or configure at run-time the architectural template to address a variable workload.nThe 2PARMA project aims at overcoming the lack of parallel programming models and run-time resource management techniques to exploit the features of many-core processor architectures. To this purpose, a proper Consortium has been set up to gather the required expertise in the areas of system/application software and computing architectures.The 2PARMA project focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable bytecode, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics.