SMART MEMORY SYSTEM

HARDWARE AND SOFTWARE TECHNIQUES TO IMPROVE MEMORY SYSTEM PERFORMANCE AND POWER ON MULTICORE ARCHITECTURES

Coordinatore	ASELSAN Elektronik Sanayi ve Ticaret A.S.    more  Organization address address: MEHMET AKIF ERSOY MAHALLESI 296 CADDE 16 city: YENIMAHALLE ANKARA postcode: 6172 contact info Titolo: Dr. Nome: Cengiz Cognome: Erbas Email: send email Telefono: 903128000000 Fax: 903128000000
Nazionalità Coordinatore	Turkey [TR]
Totale costo	100˙000 €
EC contributo	100˙000 €
Programma	FP7-PEOPLE Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
Code Call	FP7-PEOPLE-2009-RG
Funding Scheme	MC-IRG
Anno di inizio	2011
Periodo (anno-mese-giorno)	2011-01-03   -   2016-01-03

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	ASELSAN Elektronik Sanayi ve Ticaret A.S.  Organization address address: MEHMET AKIF ERSOY MAHALLESI 296 CADDE 16 city: YENIMAHALLE ANKARA postcode: 6172 contact info Titolo: Dr. Nome: Cengiz Cognome: Erbas Email: send email Telefono: 903128000000 Fax: 903128000000	TR (YENIMAHALLE ANKARA)	coordinator	100˙000.00

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 Obiettivo del progetto (Objective)

'The proposed project, Smart Memory System, introduces novel hardware and software techniques to improve performance and power of memory systems in multicore architectures. We will develop low-cost and practical hardware techniques to enhance the memory controllers to improve memory bandwidth, latency, and power consumption, and software techniques to improve locality. The project specifically intends to meet the following scientific and technical goals: (1) creating a cycle-accurate simulation environment to design and evaluate hardware and software techniques for multicore systems, (2) developing innovative memory prefetching, memory scheduling, and memory power management techniques for multicore architectures, and developing compiler transformations to improve locality in multicore systems, and (3) integrating and evaluating hardware and software methods in the context of the multicore Cell Broadband Engine Architecture.'