CIC

Reliable Communication in Integrated Circuits

Coordinatore	more  Organization address address: The Old Schools, Trinity Lane city: CAMBRIDGE postcode: CB2 1TN contact info Titolo: Mr. Nome: Keith Cognome: Cann Email: send email Telefono: +44 1223 765418 Fax: +44 1223 332988
Nazionalità Coordinatore	Non specificata
Totale costo	165˙040 €
EC contributo	165˙040 €
Programma	FP7-PEOPLE Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
Code Call	FP7-
Anno di inizio	2010
Periodo (anno-mese-giorno)	2010-06-01   -   2012-05-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE  Organization address address: The Old Schools, Trinity Lane city: CAMBRIDGE postcode: CB2 1TN contact info Titolo: Mr. Nome: Keith Cognome: Cann Email: send email Telefono: +44 1223 765418 Fax: +44 1223 332988	UK (CAMBRIDGE)	coordinator	165˙040.80

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 Obiettivo del progetto (Objective)

'Interconnects responsible for the communication between different parts of a microprocessor are a critical bottleneck in integrated circuits. Indeed, as circuit geometries become smaller, the cost of performing computation continues to decrease while the cost of on-chip communication is not improving. The conventional approach to address this bottleneck is to introduce new materials and refine manufacturing technology of integrated circuits so as to reduce performance limiting effects in interconnects. However, it is expected that to address long-term technology requirements of integrated circuits new design or technology solutions will be needed. One possible solution that addresses performance limitations of interconnects is to use signal coding techniques. Thus, instead of sending data directly from one part of a microprocessor to another, they are first encoded so as to protect them against physical disturbances. This has the advantage that current interconnect technology can be used. However, designing good coding techniques involves the optimization of numerous design parameters and is therefore a challenging task. The proposed project addresses the design of coding techniques for on-chip communication by studying interconnects from an information-theoretic perspective. The following objectives shall be pursued: to identify the main physical phenomena that limit interconnect performance and to propose a channel model; to determine the largest code rate that allows for reliable on-chip communication (information theorists refer to this rate as the channel capacity); and to provide design criteria for designing coding techniques that perform close to this rate. The conclusions that can be drawn from these analyses will help future integrated circuit designers to address performance limitations of interconnects.'