PRESTO
ImProvements of industrial Real Time Embedded SysTems devel0pment process
| Coordinatore | TELETEL TECHNOLOGIA TILEPIKOINONION KAI PLIROFORIKIS ANONYMI EMPORIKI VIOMICHANIKI ETAIREIA
Organization address
address: KIFISSIAS AVENUE 124 contact info |
| Nazionalità Coordinatore | Greece [EL] |
| Totale costo | 7˙757˙834 € |
| EC contributo | 1˙295˙558 € |
| Programma | FP7-JTI
Specific Programme "Cooperation": Joint Technology Initiatives |
| Code Call | ARTEMIS-2010-1 |
| Funding Scheme | JTI-CP-ARTEMIS |
| Anno di inizio | 2011 |
| Periodo (anno-mese-giorno) | 2011-04-01 - 2014-05-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
TELETEL TECHNOLOGIA TILEPIKOINONION KAI PLIROFORIKIS ANONYMI EMPORIKI VIOMICHANIKI ETAIREIA
Organization address
address: KIFISSIAS AVENUE 124 contact info |
EL (ATHINA) | coordinator | 0.00 |
| 2 |
SOFTEAM
Organization address
address: Avenue Victor Hugo 21 contact info |
FR (PARIS) | participant | 253˙814.95 |
| 3 |
THALES COMMUNICATIONS & SECURITY SAS
Organization address
address: AVENUE DES LOUVRESSES 4 contact info |
FR (GENNEVILLIERS) | participant | 231˙231.38 |
| 4 |
Thales Italia spa
Organization address
address: VIA PROVINCIALE LUCCHESE 33 contact info |
IT (milan) | participant | 200˙400.00 |
| 5 |
Teknologian tutkimuskeskus VTT Oy
Organization address
address: Vuorimiehentie 3 contact info |
FI (Espoo) | participant | 155˙658.19 |
| 6 | Metacase Consulting Oy | FI | participant | 100˙200.00 |
| 7 |
UNIVERSITA DEGLI STUDI DI L'AQUILA
Organization address
address: PIAZZA VINCENZO RIVERA 1 contact info |
IT (L'AQUILA) | participant | 86˙572.80 |
| 8 |
SAROKAL SOLUTIONS OY
Organization address
address: VALTATIE 67 contact info |
FI (OULU) | participant | 71˙954.96 |
| 9 |
PRISMTECH LIMITED
Organization address
address: "PRISMTECH HOUSE 5TH AVENUE BUSINESS PARK, TEAM VALLEY" contact info |
UK (GATESHEAD) | participant | 58˙181.63 |
| 10 |
RAPITA SYSTEMS LIMITED
Organization address
address: "ITCENTER,YORK SCIENCE PARK,HESLINGTON YORK" contact info |
UK (YORK) | participant | 52˙552.73 |
| 11 |
PRAGMADEV SARL
Organization address
address: RUE SAINT AMBROISE 9 contact info |
FR (PARIS) | participant | 49˙634.07 |
| 12 |
INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE
Organization address
address: Domaine de Voluceau, Rocquencourt contact info |
FR (LE CHESNAY Cedex) | participant | 35˙357.57 |
| 13 |
MILTECH HELLAS AE
Organization address
address: METAXA STREET 90 contact info |
EL (PEANIA) | participant | 0.00 |
| 14 |
TEKNOLOGIAN TUTKIMUSKESKUS VTT
Organization address
address: TEKNIIKANTIE 4 A contact info |
FI (ESPOO) | participant | 0.00 |
Mappa
Word cloud
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
Obiettivo del progetto (Objective)
'The PRESTO project aims at improving test-based embedded systems development and validation, while considering the constraints of industrial development processes. This project is based on the integration of (a) test traces exploitation (generated by test execution in the software integration phase induced by the industrial development process, to validate the requirements of the system) along with (b) platform models and (c) design space exploration techniques. The expected result of the project is to enable functional and performance analysis and platform optimisation at early stage of the design development. The approach of PRESTO is to model the software/hardware allocation, by the use of a modelling framework based on the UML profile for model-driven development of Real Time and Embedded Systems (MARTE). The analysis tools, among them timing analysis including Worst Case Execution Time (WCET) analysis, scheduling analysis and possibly more abstract system-level timing analysis techniques will receive as inputs on the one hand information from the MARTE performance modelling of the HW/SW-platform, and on the other hand behavioural information of the software design from tests results of the integration test execution. Of particular novelty in PRESTO is the exploitation of traces for the exclusion of over-pessimistic assumptions during timing analysis: instead of taking all possible inputs and states into account for a worst-case analysis, a set of relevant traces is analyzed separately to reduce the set of possible inputs and states for each trace.
A particular attention will be given to industrial development constraints, which means 1) as little cost as possible in term of extra specification time and need of expertise, 2) a simple use of the tools, 3) a smooth integration in the current design process, 4) a tool framework flexible enough to be adapted to different process methodologies, design languages and integration test frameworks, 5) analysis results
DoW (TA) Approved by the ARTEMIS JU on 26/05/2014'