PASTRY
Phase Change Memory Advanced universal Switches through Thin alteRnating laYers
| Coordinatore | MICRON SEMICONDUCTOR ITALIA SRL
Organization address
address: VIA CAMILLO OLIVETTI 2 contact info |
| Nazionalità Coordinatore | Italy [IT] |
| Totale costo | 4˙400˙621 € |
| EC contributo | 3˙067˙901 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2011-8 |
| Funding Scheme | CP |
| Anno di inizio | 2012 |
| Periodo (anno-mese-giorno) | 2012-10-01 - 2015-09-30 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
MICRON SEMICONDUCTOR ITALIA SRL
Organization address
address: VIA CAMILLO OLIVETTI 2 contact info |
IT (AGRATE BRIANZA) | coordinator | 0.00 |
| 2 |
ELETTRA - SINCROTRONE TRIESTE SCPA
Organization address
address: SS 14 KM contact info |
IT (BASOVIZZA TRIESTE) | participant | 0.00 |
| 3 |
FORSCHUNGSVERBUND BERLIN E.V.
Organization address
address: Rudower Chaussee contact info |
DE (BERLIN) | participant | 0.00 |
| 4 |
RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHEN
Organization address
address: Templergraben contact info |
DE (AACHEN) | participant | 0.00 |
| 5 |
RIJKSUNIVERSITEIT GRONINGEN
Organization address
address: Broerstraat contact info |
NL (GRONINGEN) | participant | 0.00 |
| 6 |
THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
Organization address
address: The Old Schools, Trinity Lane contact info |
UK (CAMBRIDGE) | participant | 0.00 |
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Obiettivo del progetto (Objective)
Charge storage has been the main physical mechanism supporting all solid state mass storage memories until now, both DRAM and FLASH. However none of the two main memory types appear to fully satisfy system requirements, DRAM because of its volatility and large power dissipation, and FLASH because of its slow programming speed and large block organization. PCM technology is a promising candidate to target the 'universal memory' matching most of the properties of FLASH and DRAM. However, to realize the full potential of PCM two crucial memory characteristics have to be improved: programming current and switching speed.The new memory concept investigated in the project is based on engineered Chalcogenide SuperLattices (CSL) that should allow realizing the memory switching with a modification in the bonding nature instead of the energy expensive melting process, bringing about a significant reduction of both transition times and programming currents. Despite the convincing experimental evidence the physical mechanism is not yet understood.The project aims at exploiting the potential of CSL-PCM memory cells, starting from an atomistic understanding of switching in CSL materials through experiments and physical model development, leading to new insights for CSL engineering. Optimization of the CSL device will be achieved through the development of a test vehicle allowing the benchmark among different stacks, based on 'universal memory' electrical performance targets. A large array, realized at 2X technology node, will be fabricated and integration issues will be addressed. Scalability to the 1X node will be also evaluated to demonstrate the capability to become a real 'universal memory' also for the next generations of memory chips.At the end of the project a first 'universal memory' chip at the state of the art technology node will be available with an expected direct impact on the solid state memory market.