MECCA

Meeting Challenges in Computer Architecture

Coordinatore	CHALMERS TEKNISKA HOEGSKOLA AB    more Spiacenti, non ci sono informazioni su questo coordinatore. Contattare Fabio per maggiori infomrazioni, grazie.
Nazionalità Coordinatore	Sweden [SE]
Totale costo	2˙379˙822 €
EC contributo	2˙379˙822 €
Programma	FP7-IDEAS-ERC Specific programme: "Ideas" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
Code Call	ERC-2013-ADG
Funding Scheme	ERC-AG
Anno di inizio	2014
Periodo (anno-mese-giorno)	2014-02-01   -   2019-01-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	CHALMERS TEKNISKA HOEGSKOLA AB  Organization address address: - city: GOETEBORG postcode: 41296 contact info Titolo: Mr. Nome: Axel Cognome: Persson Email: send email Telefono: +46 31 7723585	SE (GOETEBORG)	hostInstitution	2˙379˙822.00
2	CHALMERS TEKNISKA HOEGSKOLA AB  Organization address address: - city: GOETEBORG postcode: 41296 contact info Titolo: Prof. Nome: Per Orvar Cognome: Stenström Email: send email Telefono: +46 31 772 1761 Fax: +46 31 7723663	SE (GOETEBORG)	hostInstitution	2˙379˙822.00

Mappa

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 Obiettivo del progetto (Objective)

'Computer technology has doubled computational performance every 24 months, over the past several decades. This performance growth rate has been an enabler for the dramatic innovation in information technology that now embraces our society. Before 2004, application developers could exploit this performance growth rate with no effort. However, since 2004 power consumption of computer chips exceeded the allowable limits and from that point and onwards, parallel computer architectures became the norm. Currently, parallelism is completely exposed to application developers and managing it is difficult and time-consuming. This has a serious impact on software productivity that may stall progress in information technology.

Technology forecasts predict that by 2020 there will be hundreds of processors on a computer chip. Apart from managing parallelism, keeping power consumption within allowable limits will remain a key roadblock for maintaining historical performance growth rates. Power efficiency must increase by an order of magnitude in the next ten years to not limit the growth rate. Finally, computer chips are also key components in embedded controllers, where stringent timing responses are mandatory. Delivering predictable and tight response times using parallel architectures is a challenging and unsolved problem.

MECCA takes a novel, interdisciplinary and unconventional approach to address three important challenges facing computer architecture – the three Ps: Parallelism, Power, and Predictability in a unified framework. Unlike earlier, predominantly disciplinary approaches, MECCA bridges layers in computing systems from the programming language/model, to the compiler, to the run-time/OS, down to the architecture layer. This opens up for exchanging information across layers to manage parallelism and architectural resources in a transparent way to application developers to meet challenging performance, power, and predictability requirements for future computers.'