Apple-CORE
Architecture Paradigms and Programming Languages for Efficient programming of multiple CORES
| Coordinatore | UNIVERSITEIT VAN AMSTERDAM
Organization address
address: Kruislaan 404 contact info |
| Nazionalità Coordinatore | Netherlands [NL] |
| Totale costo | 2˙751˙973 € |
| EC contributo | 2˙099˙994 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2007-1 |
| Funding Scheme | CP |
| Anno di inizio | 2007 |
| Periodo (anno-mese-giorno) | 2007-11-01 - 2011-04-30 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
UNIVERSITEIT VAN AMSTERDAM
Organization address
address: Kruislaan 404 contact info |
NL (Amsterdam) | coordinator | 0.00 |
| 2 |
ACE ASSOCIATED COMPILER EXPERTS B.V.
Organization address
address: DE RUYTERKADE 113 contact info |
NL (AMSTERDAM) | participant | 0.00 |
| 3 |
AEROFLEX GAISLER AB
Organization address
address: KUNGSGATAN contact info |
SE (GOTEBORG) | participant | 0.00 |
| 4 |
PANEPISTIMIO IOANNINON
Organization address
address: LEOFOROS STAVROS S NIARCHOS, PANEPISTIMIOUPOLI IOANNINON contact info |
EL (IOANNINA) | participant | 0.00 |
| 5 |
THE UNIVERSITY OF HERTFORDSHIRE HIGHER EDUCATION CORPORATION
Organization address
address: COLLEGE LANE contact info |
UK (HATFIELD) | participant | 0.00 |
| 6 |
USTAV TEORIE INFORMACE A AUTOMATIZACE AV CR, v.v.i.
Organization address
address: POD VODARENSKOU VEZI contact info |
CZ (PRAHA) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
Apple-CORE will develop compilers, operating systems and execution platforms to support and evaluate a novel architecture paradigm that can exploit many-core chips to the end of silicon. It adopts a systematic model of concurrency implemented as instructions in the processors' ISA (developed in the EU FP6 AETHER project). This has enormous potential but is disruptive, as this paradigm shift requires a new infrastructure of tools. The benefits are large, however, as compilers need only capture concurrency in a virtual way rather than capturing, mapping and scheduling it. This separates the concerns of programming and concurrency engineering and opens the door for successful parallelising compilers. Mapping and scheduling is performed dynamically by implementations of the concurrency control instructions in the processors ISA. Another advantage of this approach is its binary compatibility. This means backward compatibility over a base ISA and forward compatibility as compiled code is executable on an arbitrary numbers of processors. Ths compatibility also enables dynamic resource mapping to binary programs from a pool of processors. Particular benefits can be expected for data-parallel and functional programming languages as they expose concurrency in a way that can easily be captured by a compiler. As well as computational benefit the ISA supports the management of partial failure, which provides support for reliable systems. Finally, this approach exposes information about the work to be executed on each processor and how much can be executed at any given time. This information can provide powerful mechanisms for the management of power by load balancing processors based on clock/ frequency scaling. The objective of developing this infrastructure is to evaluate the model and provide opportunities to exploit the results of this research in a variety of markets, including embedded and commodity processors, and also high-performance applications.