Coordinatore | MICRON SEMICONDUCTOR ITALIA SRL
Organization address
address: Contrada Blocco Torrazze Zona Industriale Sud contact info |
Nazionalità Coordinatore | Italy [IT] |
Totale costo | 3˙209˙639 € |
EC contributo | 1˙849˙337 € |
Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
Code Call | FP7-ICT-2007-1 |
Funding Scheme | CP |
Anno di inizio | 2008 |
Periodo (anno-mese-giorno) | 2008-01-01 - 2010-03-31 |
# | ||||
---|---|---|---|---|
1 |
MICRON SEMICONDUCTOR ITALIA SRL
Organization address
address: Contrada Blocco Torrazze Zona Industriale Sud contact info |
IT (Catania) | coordinator | 0.00 |
2 |
AGILENT TECHNOLOGIES BELGIUM NV
Organization address
address: DE KLEETLAAN 12A contact info |
BE (DIEGEM) | participant | 0.00 |
3 |
CADENCE DESIGN SYSTEMS GMBH
Organization address
address: MOZARTSTRASSE 2 contact info |
DE (FELDKIRCHEN) | participant | 0.00 |
4 |
INSTITUTO DE TELECOMUNICACOES
Organization address
address: AVENIDA DE ROVISCO PAIS 1 contact info |
PT (LISBOA) | participant | 0.00 |
5 |
Microwave Characterization Center SAS
Organization address
address: 61 RUE DES POSTES contact info |
FR (LILLE) | participant | 0.00 |
6 |
POLITECNICO DI TORINO
Organization address
address: CORSO DUCA DEGLI ABRUZZI 24 contact info |
IT (TORINO) | participant | 0.00 |
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
Today advanced System-in-Package(SiP) can integrate several Large-Scale-Integration(LSI) technologies and functionalities (advanced System-on-Chip-SoC),high-density memories,high-performance analogue-block.It's become strategic to analize and detect potential signal and power integrity failures before the prototype phase.The key to success is a set of integrated EDA tools and modelling flows that combine the availability of accurate models, either extracted by simulations or measurements, with reliable time-domain and system-level verification simulation methodologies.The aim is to develop reliable modelling and simulation solutions for SiP design and verification. The modelling activity will be related to measurement analysis for validating the simulation results and making available characterization measurement platforms.The research activities will be:1)Exploring innovative modelling approaches for Integrated-Circuit (IC) buffers, 3D physical structures and IC power rails beyond the current state-of-art;2)Investigating viable simulation and measurement strategies for SiP signal and power integrity analysis.The models and tools developed will be integrated in a unique EDA simulation platform and efforts will also be devoted to merge as more as possible the developed characterization measurement platforms.At the end of the project it is expected that the flows for extracting accurate simulation models will be available, together with a performing integrated EDA platform and a viable signal integrity measurement methodology. The final targets of project include:a)demonstration of the innovative IC simulation models developed and their related extraction flows by both simulation and measurement;b)the development of an innovative 3D EM field solver;c)the development of a performing SiP design and verification EDA platform;d)a demonstration of the developed signal integrity measurement techniques
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