VELOX

Velox: an integrated approach to transactional memory on multi- and many-core computers

Coordinatore	BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION    more  Organization address address: Calle Jordi Girona 31 city: BARCELONA contact info Cognome: ALIOTO, GINA Email: send email Telefono: -4138031 Fax: -4137780
Nazionalità Coordinatore	Spain [ES]
Totale costo	4˙447˙650 €
EC contributo	3˙094˙451 €
Programma	FP7-ICT Specific Programme "Cooperation": Information and communication technologies
Funding Scheme	CP
Anno di inizio	2008
Periodo (anno-mese-giorno)	2008-01-01   -   2010-12-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION  Organization address address: Calle Jordi Girona 31 city: BARCELONA contact info Cognome: ALIOTO, GINA Email: send email Telefono: -4138031 Fax: -4137780	ES (BARCELONA)	coordinator	0.00
2	AMD SAXONY LIMITED LIABILITY COMPANY & CO. KG  Organization address address: WILSCHDORFER LANDSTRASSE 101 city: DRESDEN postcode: 01 109 contact info Cognome: N/A	DE (DRESDEN)	participant	0.00
3	Chalmers Tekniska Hoegskola Aktiebolag  Organization address city: GOETEBORG postcode: 412 96 contact info Cognome: N/A	SE (GOETEBORG)	participant	0.00
4	ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE	CH	participant	0.00
5	RED HAT LIMITED  Organization address address: BUILDING 4200 CORK AIRPORT BUSINESS PARK KINSALE ROAD city: CORK contact info Cognome: N/A	IE (CORK)	participant	0.00
6	TECHNISCHE UNIVERSITAET DRESDEN	DE	participant	0.00
7	TEL AVIV UNIVERSITY	IL	participant	0.00
8	UNIVERSITE DE NEUCHATEL  Organization address address: FAUBOURG DU LAC 5A city: NEUCHATEL postcode: 2001 contact info Cognome: N/A	CH (NEUCHATEL)	participant	0.00
9	VIRTUALLOGIX SA  Organization address address: AVENUE GUSTAVE EIFFEL 6 city: MONTIGNY-LE-BRETONNEUX postcode: 78180 contact info Cognome: N/A	FR (MONTIGNY-LE-BRETONNEUX)	participant	0.00

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 Obiettivo del progetto (Objective)

The adoption of multi- and many-core chips as the architecture-of-choice for mainstream computing will undoubtedly bring about profound changes in the way software is developed. In particular, the use of fine grained locking as the multi-core programmer's coordination methodology is viewed by most experts as a dead-end. The transactional memory (TM) programming paradigm is a strong contender to become the approach of choice for replacing locks and implementing atomic operations in concurrent programming.

Combining sequences of concurrent operations into atomic transactions promises a great reduction in the complexity of both programming and verification, by making parts of the code appear to be sequential without the need to program fine-grained locks. Transactions remove from the programmer the burden of figuring out the interaction among concurrent operations that happen to conflict when accessing the same locations in memory.

To make TM an effective tool, TM systems will need the right hardware and software support to provide scalability not only in terms of number of cores, but also in terms of code size and complexity. The objective of this project is to understand how to provide such support by developing an integrated TM stack. Such a TM stack would span a system from the underlying hardware to the high end application and would consist of the following components: CPU, operating system, runtime, libraries, compilers, programming languages and application environments.

We anticipate that such a fully integrated TM system will not only improve our understanding of TM designs but also greatly help in the adoption of the TM paradigm by the European software industry, making it a tool-of-choice for concurrent programming on multi- and many-core platforms.