GNOC

Towards a Gaussian Network-on-Chip

 Coordinatore TECHNION - ISRAEL INSTITUTE OF TECHNOLOGY 

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 Nazionalità Coordinatore Israel [IL]
 Totale costo 582˙500 €
 EC contributo 582˙500 €
 Programma FP7-IDEAS-ERC
Specific programme: "Ideas" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
 Code Call ERC-2007-StG
 Funding Scheme ERC-SG
 Anno di inizio 2008
 Periodo (anno-mese-giorno) 2008-08-01   -   2012-07-31

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    TECHNION - ISRAEL INSTITUTE OF TECHNOLOGY

 Organization address address: TECHNION CITY - SENATE BUILDING
city: HAIFA
postcode: 32000

contact info
Titolo: Dr.
Nome: Isaac
Cognome: Keslassy
Email: send email
Telefono: -8294770
Fax: -8294789

IL (HAIFA) hostInstitution 0.00
2    TECHNION - ISRAEL INSTITUTE OF TECHNOLOGY

 Organization address address: TECHNION CITY - SENATE BUILDING
city: HAIFA
postcode: 32000

contact info
Titolo: Mr.
Nome: Mark
Cognome: Davison
Email: send email
Telefono: +972 4 829 3097
Fax: +972 4 823 2958

IL (HAIFA) hostInstitution 0.00

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

chip    noc    argue    guarantees    models    processor    architectures    deterministic    patterns    unreliable    traffic    designers    qos    delays    benchmarks   

 Obiettivo del progetto (Objective)

'As chip multi-processor architectures are replacing single-processor architectures and reshaping the semiconductor industry, chip designers can hardly use their old models and benchmarks anymore. While designers were used to deterministic and reliable performance in the chips, they now face networks with unreliable traffic patterns, unreliable throughput and unreliable delays, hence making it hard to provide any guaranteed Quality-of-Service (QoS). In this proposal, we argue that chip designers should focus on the possible set of traffic patterns in their Network-on-Chip (NoC) architectures. We first show how to provide deterministic QoS guarantees by exploiting these patterns. Then, we explain why the cost of providing deterministic guarantees might become prohibitive, and defend an alternative statistical approach that can significantly lower the area and power. To do so, we introduce Gaussian-based NoC models, and show how they can be used to evaluate link loads, delays and throughputs, as well as redesign the routing and capacity allocation algorithms. Finally, we argue that these models could effectively complement current benchmarks, and should be a central component in the toolbox of the future NoC designer.'

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