HTCMP
Heterogeneous Chip Multiprocessor Design
| Coordinatore |
Organization address
address: ESKISEHIR YOLU 8 KM contact info |
| Nazionalità Coordinatore | Non specificata |
| Totale costo | 100˙000 € |
| EC contributo | 100˙000 € |
| Programma | FP7-PEOPLE
Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013) |
| Code Call | FP7-PEOPLE-IRG-2008 |
| Funding Scheme | MC-I |
| Anno di inizio | 2009 |
| Periodo (anno-mese-giorno) | 2009-04-01 - 2013-03-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
Nome Ente NON disponibile
Organization address
address: ESKISEHIR YOLU 8 KM contact info |
TR (ANKARA) | coordinator | 100˙000.00 |
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Obiettivo del progetto (Objective)
'Increasing complexity of applications and their large dataset sizes make it imperative to consider novel architectures that are efficient from both performance and power angles. Chip Multiprocessors (CMP) are one such example where multiple processor cores are placed into the same die. As technology scales, the International Technology Roadmap for Semiconductors (ITRS) projects that the number of cores in a chip multiprocessor (CMP) will drastically increase to satisfy performance requirements of future applications. A critical question that needs to be answered in CMPs is the size and strength of the cores. Homogeneous chip multiprocessors provide only one type of core to match these various application requirements, consequently not fully utilizing the available chip area and power budget. The ability to dynamically switch between different cores, and power down unused cores gives a key advantage to heterogeneous chip multiprocessing. One of the challenging problems in the context of heterogeneous chip multiprocessor systems is the placement of processor cores and storage blocks within the available chip area. Focusing on such a heterogeneous chip multiprocessor, we address different design decision problems. First, decide on the memory hierarchy design and its distribution within the available chip area. Second, distribute effectively the available area among the processor cores and the memory blocks (cache). Third, select the optimum number of processors and their types among the available processor types. Fourth, perform thread and data distribution within the given processor and memory design. Fifth, evaluate improvements brought by advanced techniques, such as 3D designs. Our past experience and preliminary results indicate that the proposed approach will be able to generate promising results.'