THREEDSURFACE

"Three-Dimensional Surface Nano-Patterning: Concepts, Challenges and Applications"

 Coordinatore TECHNISCHE UNIVERSITAET ILMENAU 

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 Nazionalità Coordinatore Germany [DE]
 Totale costo 1˙398˙600 €
 EC contributo 1˙398˙600 €
 Programma FP7-IDEAS-ERC
Specific programme: "Ideas" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
 Code Call ERC-2009-StG
 Funding Scheme ERC-SG
 Anno di inizio 2009
 Periodo (anno-mese-giorno) 2009-09-01   -   2015-06-30

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    WESTFAELISCHE WILHELMS-UNIVERSITAET MUENSTER

 Organization address address: SCHLOSSPLATZ 2
city: MUENSTER
postcode: 48149

contact info
Titolo: Dr.
Nome: Katharina
Cognome: Steinberg
Email: send email
Telefono: 492518000000
Fax: 492518000000

DE (MUENSTER) beneficiary 389˙748.25
2    TECHNISCHE UNIVERSITAET ILMENAU

 Organization address address: EHRENBERGSTRASSE 29
city: ILMENAU
postcode: 98693

contact info
Titolo: Mr.
Nome: Thomas
Cognome: Mirow
Email: send email
Telefono: +49 3677 69 2555
Fax: +49 3677 69 1596

DE (ILMENAU) hostInstitution 1˙008˙851.75
3    TECHNISCHE UNIVERSITAET ILMENAU

 Organization address address: EHRENBERGSTRASSE 29
city: ILMENAU
postcode: 98693

contact info
Titolo: Prof.
Nome: Yong
Cognome: Lei
Email: send email
Telefono: +49 3677 69 3748
Fax: +49 3677 69 3746

DE (ILMENAU) hostInstitution 1˙008˙851.75

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

patterning    area    dimensional    nanomaterials    structures    property    attractive    surface    semiconductor    patterns    extremely    nanostructures    synthesized    nano    advantages   

 Obiettivo del progetto (Objective)

'Multifunctional surface nano-patterns on substrates are the foundation of semiconductor nano-devices. There is a major shortcoming of the existing surface nano-patterning techniques - in fact almost all synthesized surface patterns are two-dimensional (2-D) planar structures with low aspect ratio. Thus one of the most attractive advantages of nanomaterials, an extremely large surface area, is missing in the existing 2-D surface nano-patterns. This largely limits the application potential of surface nanostructures on semiconductor devices. In this project, a new concept of three-dimensional (3-D) nano-patterning is proposed. Using this multi-functional 3-D surface nano-patterning technique, large-scale surface patterns of well-defined one-dimensional (1-D) nanostructures can be synthesized by different fabrication strategies. The realization of the 3-D surface nano-patterning will not only retain the attractive features of the conventional 2-D surface nano-patterning (e.g. high patterning density), but also bring back one of the basic advantages of nanomaterials, i.e. an extremely large surface area. Using an innovative addressing system proposed in this project, it is possible to investigate and analyze the properties of an individual unit within a regular surface nanostructure array and the coupling interaction between the adjacent units. By integrating these data, the properties of the whole ensembles could be obtained. This bottom-up investigation might pave the way to a complete property tuning based on the structural design of surface 1-D nanostructures. The large-scale 1-D surface nano-patterns with well-defined structures have broad application potentials for different high-performance and property-controllable nano-devices.'

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