HEAP

A Highly Efficient Adaptive Multi-processor Framework

Coordinatore	STMICROELECTRONICS SRL    more  Organization address address: VIA C.OLIVETTI 2 city: AGRATE BRIANZA postcode: 20864 contact info Titolo: Dr. Nome: MARIA GRAZIA Cognome: PODESTA' Email: send email Telefono: +39 039 6037255 Fax: +39 039 6035910
Nazionalità Coordinatore	Italy [IT]
Totale costo	3˙319˙323 €
EC contributo	2˙216˙069 €
Programma	FP7-ICT Specific Programme "Cooperation": Information and communication technologies
Code Call	FP7-ICT-2009-4
Funding Scheme	CP
Anno di inizio	2010
Periodo (anno-mese-giorno)	2010-02-01   -   2013-01-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	STMICROELECTRONICS SRL  Organization address address: VIA C.OLIVETTI 2 city: AGRATE BRIANZA postcode: 20864 contact info Titolo: Dr. Nome: MARIA GRAZIA Cognome: PODESTA' Email: send email Telefono: +39 039 6037255 Fax: +39 039 6035910	IT (AGRATE BRIANZA)	coordinator	0.00
2	ACE ASSOCIATED COMPILER EXPERTS B.V.  Organization address address: DE RUYTERKADE 113 city: AMSTERDAM postcode: 1011AB contact info Titolo: Mr. Nome: Marius Cognome: Schoorel Email: send email Telefono: +31 20 6646416 Fax: +31 20 6750389	NL (AMSTERDAM)	participant	0.00
3	ATHENA RESEARCH AND INNOVATION CENTER IN INFORMATION COMMUNICATION & KNOWLEDGE TECHNOLOGIES  Organization address address: ARTEMIDOS 6 KAI EPIDAVROU city: MAROUSSI postcode: 151 25 contact info Titolo: Prof. Nome: Dimitrios Cognome: Serpanos Email: send email Telefono: 302611000000 Fax: 302611000000	EL (MAROUSSI)	participant	0.00
4	COMPAAN DESIGN BV  Organization address address: GALILEIWEG city: LEIDEN postcode: 2333BD contact info Titolo: Dr. Nome: Bart Cognome: Kienhuis Email: send email Telefono: 31612548219 Fax: +31 71 301 5886	NL (LEIDEN)	participant	0.00
5	POLITECNICO DI TORINO  Organization address address: CORSO DUCA DEGLI ABRUZZI city: TORINO postcode: 10129 contact info Titolo: Ms. Nome: Roberta Cognome: Melchiorre Email: send email Telefono: +39 011 5644188 Fax: +39 011 5644099	IT (TORINO)	participant	0.00
6	SINGULARLOGIC ANONYMI ETAIRIA PLIROFORIAKON SISTIMATON KAI EFARMOGON PLIROFORIKIS  Organization address address: AL.PANAGOULI & SINIOSOGLOU city: NEA IONIA, ATHENS postcode: 14234 contact info Titolo: Mrs. Nome: Evelina Cognome: Peristeri Email: send email Telefono: +30 210 6266262 Fax: +30 210 6266210	EL (NEA IONIA, ATHENS)	participant	0.00
7	SYNELIXIS LYSEIS PLIROFORIKIS AUTOMATISMOU & TILEPIKOINONION MONOPROSOPI EPE  Organization address address: FARMAKIDOU 10 city: CHALKIDA postcode: 34100 contact info Titolo: Dr. Nome: Ioannis Cognome: Papaefstathiou Email: send email Telefono: 306944000000 Fax: 302221000000	EL (CHALKIDA)	participant	0.00
8	THALES COMMUNICATIONS & SECURITY SAS  Organization address address: Boulevard de Valmy city: COLOMBES postcode: 92700 contact info Titolo: Dr. Nome: Sylvie Cognome: RAYNAUD Email: send email Telefono: +33 1 46 13 26 42 Fax: 33146133280	FR (COLOMBES)	participant	0.00
9	UNIVERSITA DEGLI STUDI DI GENOVA  Organization address address: VIA BALBI city: GENOVA postcode: 16126 contact info Titolo: Dr. Nome: Franco Cognome: Gabrielli Email: send email Telefono: +39 0103532274 Fax: +39 0103532036	IT (GENOVA)	participant	0.00
10	UPPSALA UNIVERSITET  Organization address address: St Olofsgatan city: UPPSALA postcode: 751 05 contact info Titolo: Mr. Nome: Patrik Cognome: Armuand Email: send email Telefono: 46184715701 Fax: 4618511925	SE (UPPSALA)	participant	0.00

Mappa

 Word cloud

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 Obiettivo del progetto (Objective)

Writing parallel programs has traditionally been considered a difficult task, even when parallelism is taken into account from the beginning. Moreover there is an urgent need to parallelize the massive amounts of legacy sequential code so as to increase its performance on processors and systems that refocus from single-thread acceleration to increasing the overall throughput. At the same time, memory (in particular cache) performance is essential to achieve the full gain from a parallelized application. However, while processor architecture tends to be relatively standard across applications within a domain, huge performance and power improvements can be achieved by tailoring the cache architecture to the application at hand, and not just to an entire domain.nnThe HEAP project faces these challenges directly, by developing:n1.tAn innovative toolset that helps software developers profile and parallelize existing sequential implementations by exploiting top-level pipeline-style parallelism.n2.tA highly configurable cache architecture that can be tailored to an application by using the same profiling data as those that were used for parallelization, in order to fully exploit the available computing power.nnIn particular, the HEAP project will providen1.ta novel SMP multicore platform supporting a group of novel cache coherence protocols; each application will be profiled so as to select and tune the most appropriate cache coherency mechanism.n2.tan innovative toolflow that complements this architecture; this tool will ease and/or automate the parallelisation of sequential C-code based on an analysis of the dataflow while it will provide configuration and tuning data (e.g. in terms of which variables are local, and which are mostly written or mostly read by a thread) to the cache coherency mechanisms so as to optimize them for the given applicationnnIn order to increase the exploitability of the end-results, the toolflow (an incarnation of which will be also distributed in an open source manner) will be implemented in such a way that it will be able to perform sequential-to-multicore migration for any multicore architecture (not only the HEAP one). Moreover, the architecture will be capable of running multithreaded code compiled by any compiler/toolset (not only the one implemented by HEAP). However, in order to take full advantage of the HEAP results, the combined toolset and architecture should be utilized.nnWe innovate in the first domain by using both pessimistic and optimistic estimates of the available parallelism, by refining those estimates using metric-driven verification techniques, and by supporting dynamic recovery of excessively optimistic parallelization.