Coordinatore | UNIVERSITA' DEGLI STUDI DI SIENA
Organization address
address: Via Roma c/o INGEGNERIA 56 contact info |
Nazionalità Coordinatore | Italy [IT] |
Totale costo | 8˙207˙282 € |
EC contributo | 6˙120˙000 € |
Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
Code Call | FP7-ICT-2009-4 |
Funding Scheme | CP |
Anno di inizio | 2010 |
Periodo (anno-mese-giorno) | 2010-01-01 - 2014-03-31 |
# | ||||
---|---|---|---|---|
1 |
UNIVERSITA' DEGLI STUDI DI SIENA
Organization address
address: Via Roma c/o INGEGNERIA 56 contact info |
IT (SIENA) | coordinator | 0.00 |
2 |
Nome Ente NON disponibile
Organization address
address: CL Vicente Aleixandre 1 contact info |
ES (MADRID) | participant | 0.00 |
3 |
BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Calle Jordi Girona 31 contact info |
ES (BARCELONA) | participant | 0.00 |
4 |
CAPS entreprise
Organization address
city: Rennes contact info |
FR (Rennes) | participant | 0.00 |
5 |
INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE
Organization address
address: Domaine de Voluceau, Rocquencourt contact info |
FR (LE CHESNAY Cedex) | participant | 0.00 |
6 |
MICROSOFT ISRAEL RESEARCH AND DEVELOPMENT 2002 LTD
Organization address
address: SHENKAR STREET 13 GEV YAM BUILD 5 contact info |
IL (HERZELIA PITUACH) | participant | 0.00 |
7 |
THALES SA
Organization address
address: Rue de Villiers 45 contact info |
FR (NEUILLY SUR SEINE) | participant | 0.00 |
8 |
THE UNIVERSITY OF MANCHESTER
Organization address
address: OXFORD ROAD contact info |
UK (MANCHESTER) | participant | 0.00 |
9 |
UNIVERSITAET AUGSBURG
Organization address
address: UNIVERSITAETSSTRASSE 2 contact info |
DE (AUGSBURG) | participant | 0.00 |
10 |
UNIVERSITY OF CYPRUS
Organization address
address: KALLIPOLEOS STREET 75 contact info |
CY (NICOSIA) | participant | 0.00 |
11 |
UNIVERSITY OF DELAWARE CORPORATION
Organization address
address: HULLIHEN HALL 112 contact info |
US (Newark) | participant | 0.00 |
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
Dataflow parallelism is key to reach power efficiency, reliability, efficient parallel programmability, scalability, data bandwidth. In this project we propose dataflow both at task level and inside thenthreads, to offload and manage accelerated codes, to localize the computation, for managing the fault information with appropriate protocols, to easily migrate code to the available/working componentsnand to respect the power/performance/temperature/reliability envelope, to efficiently handle the parallelism and have an easy and powerful execution model, to produce a more predictable behavior.nWhile parallel systems have been around for many years, they were usually programmed and tuned by experts. In the future large scale systems will be widely available and therefore exploiting efficientlynthe available parallelism will have to be easy enough to be accessible by the common user. Traditional programming models are either not very efficient for every application (message passing) or difficult tonscale (shared memory). In order to address the programmability challenge we propose the use of a compiler directive based model to support an underlying dataflow-based thread execution that is known to exploit well the available parallelism and to efficiently move around large amounts of data. In particular we propose to use a model that offersndataflow scheduling of parallel execution threads. Combining multithreading with dataflow allows to exploit the available parallelism without the overheads of the original dataflow techniques.nThe multithreading dataflow model is expected to perform well for a number of classes of applications.nAn important contribution is provided by prof. Gao's team, who has been developing dataflow concepts for decades and has joined the TERAFLUX project after its initial phase.nTERAFLUX is now bringing together top experts in dataflow in both continents Europe and Americas, with the aim to reach the higher goal of demonstrating for the first time the efficiency dataflow concept for the Exascale parallel computers of the 2020 and beyond.