Synaptic
SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms
| Coordinatore | STMICROELECTRONICS SRL
Organization address
address: VIA C.OLIVETTI 2 contact info |
| Nazionalità Coordinatore | Italy [IT] |
| Totale costo | 5˙410˙613 € |
| EC contributo | 3˙520˙000 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-4 |
| Funding Scheme | CP |
| Anno di inizio | 2009 |
| Periodo (anno-mese-giorno) | 2009-11-02 - 2013-02-01 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
STMICROELECTRONICS SRL
Organization address
address: VIA C.OLIVETTI 2 contact info |
IT (AGRATE BRIANZA) | coordinator | 0.00 |
| 2 |
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Organization address
address: Kapeldreef contact info |
BE (LEUVEN) | participant | 0.00 |
| 3 |
Leading Edge S.N.C. di Vergine Pietro e Woolaway Nigel Robert
Organization address
address: VIA DELLE ATTIVITA contact info |
IT (BREMBATE) | participant | 0.00 |
| 4 |
POLITECNICO DI MILANO
Organization address
address: PIAZZA LEONARDO DA VINCI contact info |
IT (MILANO) | participant | 0.00 |
| 5 |
THALES SA
Organization address
address: Rue de Villiers contact info |
FR (NEUILLY SUR SEINE) | participant | 0.00 |
| 6 |
UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL
Organization address
address: AVENIDA PAULO GAMA contact info |
BR (PORTO ALEGRE) | participant | 0.00 |
| 7 |
UNIVERSITAT POLITECNICA DE CATALUNYA
Organization address
address: Jordi Girona contact info |
ES (BARCELONA) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
This proposal addresses Objective ICT-2009.3.2: 'Design of Semiconductor Components and Electronic Based Miniaturized Systems' by development of 'methods and tools to cope with the design challenges in the next generations of technologies' and focuses on the objective 'design for manufacturability taking into account increased variability of new processes'. The project described in this proposal targets the optimization of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels. We propose the creation of a methodology and associated suite of design tools which extract regularity at the architectural and structural level and automate the creation of regular compound cells which implement the functionality of the extracted templates. The cell creation will employ Restricted Design Rules (RDR's) and other regularity techniques at the geometrical level to maximize manufacturability and reduce systematic variations. Since the majority of designs in the nanometer regime employ some form of SRAM the project will include a study of the effects of RDR's on SRAM in terms of performance and manufacturability and the subsequent definition of a set of RDR's which allow manufacturability optimization for logic functions while remaining compatible with SRAM technologies. To this end we have assembled a consortium of European academic, research and industrial experts with world class experience in regularity approaches at the various levels. In order to ensure the successful commercialization and deployment of the resulting tool suite the consortium includes a European EDA vendor with significant expertise in the field of design optimization through automated cell creation. This project will enable European industry to play a leading role in the definition of next generation design methodologies and challenge the US domination in the area of design automation.