ENCORE
ENabling technologies for a programmable many-CORE
| Coordinatore | BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Calle Jordi Girona, Nexus II 29 contact info |
| Nazionalità Coordinatore | Spain [ES] |
| Totale costo | 3˙551˙209 € |
| EC contributo | 2˙533˙000 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-4 |
| Funding Scheme | CP |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-03-01 - 2013-02-28 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Calle Jordi Girona, Nexus II 29 contact info |
ES (Barcelona) | coordinator | 0.00 |
| 2 |
ARM LIMITED
Organization address
address: 110 FULBOURN ROAD contact info |
UK (CAMBRIDGE) | participant | 0.00 |
| 3 |
FOUNDATION FOR RESEARCH AND TECHNOLOGY HELLAS
Organization address
address: N PLASTIRA STR contact info |
EL (HERAKLION) | participant | 0.00 |
| 4 |
KUNGLIGA TEKNISKA HOEGSKOLAN
Organization address
address: Valhallavaegen contact info |
SE (STOCKHOLM) | participant | 0.00 |
| 5 |
TECHNION - ISRAEL INSTITUTE OF TECHNOLOGY
Organization address
address: Technion City-Senate Building contact info |
IL (HAIFA) | participant | 0.00 |
| 6 |
TECHNISCHE UNIVERSITAT BERLIN
Organization address
address: Strasse des 17 Juni contact info |
DE (BERLIN) | participant | 0.00 |
| 7 |
TECHNISCHE UNIVERSITEIT DELFT
Organization address
address: Stevinweg contact info |
NL (DELFT) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
Design complexity and power density implications stopped the trend towards faster single-core processors. The current trend is to double the core count every 18 months, leading to chips with 100 cores in 10-15 years. Developing parallel applications to harness such multicores is the key challenge for scalable computing systems. The ENCORE project aims at achieving a breakthrough on the usability, reliability, code portability, and performance scalability of such multicores.nThe project achieves this through three main contributions. First, defining an easy to use parallel programming model that offers code portability across several architectures. Second, developing a runtime management system that will dynamically detect, manage, and exploit parallelism, data locality, and shared resources. And third, providing adequate hardware support for the parallel programming and runtime environment that ensures scalability, performance, and cost-efficiency.nThe technology will be developed and evaluated using multiple applications, provided by the partners, or industry-standard benchmarks, ranging from massively parallel high-performance computing codes, where performance and efficiency are paramount, to embedded parallel workloads with strong real-time and energy constraints.nThe project integrates all partners under a common runtime system running on real multicore platforms, a shared FPGA architecture prototype, and a large-scale software simulated architecture. Architecture features will be validated through implementation on ARM's detailed development infrastructure.nENCORE takes a holistic approach to parallelization and programmability by analyzing the requirements of several relevant applications ranging from High Performance Computing to embedded multicore, by parallelizing these applications using the proposed programming model, by optimizing the runtime system for a range of parallel architectures, and by developing hardware support for the runtime system.