MANON

Methods for Advanced Multi-Objective Optimization for eDFY of complex Nano-scale Circuits

 Coordinatore STMICROELECTRONICS SRL 

 Organization address address: VIA C.OLIVETTI 2
city: AGRATE BRIANZA
postcode: 20864

contact info
Titolo: Mr.
Nome: Salvatore
Cognome: Rinaudo
Email: send email
Telefono: 390957000000
Fax: 390957000000

 Nazionalità Coordinatore Italy [IT]
 Totale costo 752˙481 €
 EC contributo 752˙481 €
 Programma FP7-PEOPLE
Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
 Code Call FP7-PEOPLE-2009-IAPP
 Funding Scheme MC-IAPP
 Anno di inizio 2010
 Periodo (anno-mese-giorno) 2010-10-01   -   2014-09-30

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    STMICROELECTRONICS SRL

 Organization address address: VIA C.OLIVETTI 2
city: AGRATE BRIANZA
postcode: 20864

contact info
Titolo: Mr.
Nome: Salvatore
Cognome: Rinaudo
Email: send email
Telefono: 390957000000
Fax: 390957000000

IT (AGRATE BRIANZA) coordinator 172˙296.00
2    UNIVERSITA DEGLI STUDI DI ROMA LA SAPIENZA

 Organization address address: Piazzale Aldo Moro 5
city: ROMA
postcode: 185

contact info
Titolo: Dr.
Nome: Daniela
Cognome: Padulo
Email: send email
Telefono: +39 06 44585418
Fax: +39 06 44585918

IT (ROMA) participant 271˙472.00
3    FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V

 Organization address address: Hansastrasse 27C
city: MUENCHEN
postcode: 80686

contact info
Titolo: Ms.
Nome: Andrea
Cognome: Zeumann
Email: send email
Telefono: +49 89 1205 2723
Fax: +49 89 1205772723

DE (MUENCHEN) participant 162˙362.00
4    MUNEDA GmbH

 Organization address address: Stefan-George-Ring 29
city: Munich
postcode: 81929

contact info
Titolo: Dr.
Nome: Bernd
Cognome: Lemaitre
Email: send email
Telefono: +49 89 93086347
Fax: +49 89 93086 407

DE (Munich) participant 146˙351.00

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

nano    modeling    sizes    variations    downside    circuit    performance    industrial    power    models    scaling    doping    pv    secure    optimization    techniques    yield    create    quality    statistical   

 Obiettivo del progetto (Objective)

'Cost control, production efficiency, cycle time and yield are critical quality benchmark for nanoelectronics productions. An increasingly important downside of nano-CMOS technology scaling is the fact that the scaling of feature sizes cannot be accompanied by a suitable scaling of geometric tolerances. In addition, when getting into deep miniaturized dimensions, phenomena like edges or surfaces roughness, or the fluctuation of the number of doping atoms within the channels are becoming increasingly significant. As a result, the figures of merit of a circuit, such as performance and power, have become extremely sensitive to uncontrollable statistical process variations (PV). To ensure stable manufacturability and secure high manufacturing yield, it is mandatory to manage complete design flows and to link traditional methods for design with Technology CAD models. In this context, multi-objective optimization algorithms and statistical analysis are essential on device and behavioral levels to secure high yielding by modeling the impact of inevitable process variations and doping fluctuations on IC performance. Statistical circuit modeling is a viable solution to nano-electronics production quality, on which the European Union is already investing. The project intends to create a partnership between academies, industry and SME so to create a Transfer of Knowledge between the organizations in order to pass the mathematical know how on multi-objective optimization, symbolic techniques and numerical statistical simulation on one side, the industrial design experience, real test cases availability and Electronic Design Automation (EDA) software modeling skills on the other. The scope of the research activity will be to create PV-aware and PV-robust circuit design techniques, tools and models in the frame of the analogue and mixed-signal circuit industrial design.'

Introduzione (Teaser)

The downside of scaling nanoelectronic feature sizes is increasing unreliability of performance and power (hence robustness). An EU-supported project has developed techniques to tackle this problem.

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