ULEVIS

Ultra Low Energy Vertically Integrated Circuits

Coordinatore	Sabanci University    more  Organization address address: Orhanli Tuzla city: ISTANBUL postcode: 34956 contact info Titolo: Ms. Nome: Zeynep Cognome: Birsel Email: send email Telefono: +90 216 483 9110 Fax: +90 216 483 9118
Nazionalità Coordinatore	Turkey [TR]
Totale costo	75˙000 €
EC contributo	75˙000 €
Programma	FP7-PEOPLE Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
Code Call	FP7-PEOPLE-2010-RG
Funding Scheme	MC-IRG
Anno di inizio	2010
Periodo (anno-mese-giorno)	2010-09-15   -   2013-09-14

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	Sabanci University  Organization address address: Orhanli Tuzla city: ISTANBUL postcode: 34956 contact info Titolo: Ms. Nome: Zeynep Cognome: Birsel Email: send email Telefono: +90 216 483 9110 Fax: +90 216 483 9118	TR (ISTANBUL)	coordinator	75˙000.00

Mappa

 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

 Obiettivo del progetto (Objective)

'The current integrated circuit scaling hits two major roadblocks or walls. One wall is the atomic level feature sizes of the current devices forcing the capabilities of even nano-scale implementations. The other wall is the total power consumed per unit area exceeding the capabilities thermal dissipation techniques limiting the maximum device densities. The solution to the feature size problem is scaling in the orthogonal direction to the conventional device plane - the 3D integration. The solution to the power problem is the use of ultra low power design approaches. However, the 3D integration increases the thermal dissipation problem and ultra low power design can not provide total performance due to low clock speeds unless extremely large number of devices is combined in small areas. We propose a unique combination of ultra low power design approaches and 3D integration to provide an optimal performance to the user. Low power design eliminates the thermal dissipation problem of the 3D integration whereas 3D integration enables dense device integration in small volumes to solve the space-time trade-off in ultra low power design approaches. The result will be a vertically integrated circuit with power efficiencies several hundred times better than current dedicated processors.'

Introduzione (Teaser)

EU-funded scientists proposed a novel design for integrated circuits (ICs) that can render power efficiencies several hundred times higher than current dedicated processors.