ParaPhrase
Parallel Patterns for Adaptive Heterogeneous Multicore Systems
| Coordinatore | THE UNIVERSITY COURT OF THE UNIVERSITY OF ST ANDREWS
Organization address
address: The Gateway, North Haugh contact info |
| Nazionalità Coordinatore | United Kingdom [UK] |
| Totale costo | 4˙062˙262 € |
| EC contributo | 3˙071˙999 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2011-7 |
| Funding Scheme | CP |
| Anno di inizio | 2011 |
| Periodo (anno-mese-giorno) | 2011-10-01 - 2015-03-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
THE UNIVERSITY COURT OF THE UNIVERSITY OF ST ANDREWS
Organization address
address: The Gateway, North Haugh contact info |
UK (St Andrews, Fife) | coordinator | 0.00 |
| 2 |
AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA W KRAKOWIE
Organization address
address: AL ADAMA MICKIEWICZA 30 contact info |
PL (KRAKOW) | participant | 0.00 |
| 3 |
ELTE-Soft Kutatas-Fejleszto Nonprofit Kft
Organization address
address: PAZMANY PETER SETANY 1 C contact info |
HU (BUDAPEST) | participant | 0.00 |
| 4 |
EOTVOS LORAND TUDOMANYEGYETEM
Organization address
address: EGYETEM TER 1-3 contact info |
HU (BUDAPEST) | participant | 0.00 |
| 5 |
ERLANG SOLUTIONS LIMITED
Organization address
address: BACK CHURCH LANE SUITE 2.05 NEW LOOM HOUSE 101 contact info |
UK (LONDON) | participant | 0.00 |
| 6 |
NATIONAL COLLEGE OF IRELAND
Organization address
address: MAYOR STREET IFSC contact info |
IE (DUBLIN) | participant | 0.00 |
| 7 |
SOFTWARE COMPETENCE CENTER HAGENBERG GMBH
Organization address
address: SOFTWAREPARK 21 contact info |
AT (HAGENBERG) | participant | 0.00 |
| 8 |
THE QUEEN'S UNIVERSITY OF BELFAST
Organization address
address: UNIVERSITY ROAD LANYON BUILDING contact info |
UK (BELFAST) | participant | 0.00 |
| 9 |
THE ROBERT GORDON UNIVERSITY
Organization address
address: Schoolhill contact info |
UK (ABERDEEN) | participant | 0.00 |
| 10 |
UNIVERSITA DEGLI STUDI DI TORINO
Organization address
address: Via Giuseppe Verdi 8 contact info |
IT (TORINO) | participant | 0.00 |
| 11 |
UNIVERSITA DI PISA
Organization address
address: LUNGARNO PACINOTTI 43/44 contact info |
IT (PISA) | participant | 0.00 |
| 12 |
UNIVERSITAET STUTTGART
Organization address
address: KEPLERSTRASSE 7 contact info |
DE (STUTTGART) | participant | 0.00 |
Mappa
Word cloud
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
Obiettivo del progetto (Objective)
A revolution is happening in computer hardware. After three decades during which microprocessor speeds increased almost 4000 times, we are starting to hit long-predicted physical limits on the speed of a single processor. Recent computers instead use two, four or even twelve processor cores working together ``in parallel', giving peak performance that is equivalent to a 5GHz, 10GHz or even 30GHz single processor, but at a fraction of the projected energy usage. There have even been experimental 48-core ``single cloud computer' chips giving peak performance that would exceed that of a 100GHz single processor. The effective exploitation of such high performance is essential to support modern demands for computing power in the home, in industry and in the economy at large. Combining this with low energy usage is crucial if the performance is to be delivered at a reasonable financial and environmental cost.
Future designs will harness even greater numbers of processor cores, perhaps in the thousands or millions, and perhaps with widely varying speeds and capabilities. These will be combined with advanced graphics processor units and other specialist units to give further performance and energy gains. In this way we will be able to meet society's future needs for computing power.
While there are already significant challenges in building computers, such as those described above, from heterogeneous processor and other computing units, there are even greater challenges in building parallel software that can use them effectively. In order to do this, we must produce software that is easy to write but that still allows the hardware to be used effectively.
The key innovation of the ParaPhrase project is exactly to produce such software that is easy to write using the hardware more effectively with the goal of speeding up processing by at least one order of magnitude over sequential execution on real near-term multicore architectures for the use cases and systems that will be considered in the project.
ParaPhrase will build on a (multi-level) model of parallelism, where implementations of parallel programs are expressed in terms of interacting components. By expressing parallelism in terms of high-level parallel patterns that have alternative parallel implementations, we will be able to redeploy/refactor parallel components to dynamically match the available hardware resources.
One large scale company (MELLANOX), one SME (ERLANG SOLUTIONS) and an Austrian software competence centre (SCCH) with strong links to industry will exploit the project results in a commercial context. ParaPhrase will strengthen their respective market position and competitiveness and give a manifold return on investment. The six academic partners will use the gained knowledge to enrich their teaching activities and to reinforce their prestige in the scientific community. European citizens will benefit from less power-consuming computers.