SPEAR

"Specialisable, Programmable, Efficient and Robust Microprocessors"

Coordinatore	THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE    more Spiacenti, non ci sono informazioni su questo coordinatore. Contattare Fabio per maggiori infomrazioni, grazie.
Nazionalità Coordinatore	United Kingdom [UK]
Totale costo	1˙271˙216 €
EC contributo	1˙271˙216 €
Programma	FP7-IDEAS-ERC Specific programme: "Ideas" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
Code Call	ERC-2012-StG_20111012
Funding Scheme	ERC-SG
Anno di inizio	2012
Periodo (anno-mese-giorno)	2012-09-01   -   2017-08-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE  Organization address address: The Old Schools, Trinity Lane city: CAMBRIDGE postcode: CB2 1TN contact info Titolo: Dr. Nome: Robert Cognome: Mullins Email: send email Telefono: +44 1223 763543 Fax: +44 1223 334678	UK (CAMBRIDGE)	hostInstitution	1˙271˙216.00
2	THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE  Organization address address: The Old Schools, Trinity Lane city: CAMBRIDGE postcode: CB2 1TN contact info Titolo: Ms. Nome: Renata Cognome: Schaeffer Email: send email Telefono: +44 1223 333543 Fax: +44 1223 332988	UK (CAMBRIDGE)	hostInstitution	1˙271˙216.00

Mappa

 Word cloud

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 Obiettivo del progetto (Objective)

'The development of faster, cheaper and smaller transistors has been the driving force behind the exponential growth in computing power over the past 50 years. While our ability to fabricate better transistors has not yet ceased, continuing to translate these advances into better system-level performance is now a major challenge. This proposal seeks to research a new approach to building programmable digital systems, one that can offer the efficiency, robustness and flexibility required as we approach the end of the CMOS era and start to introduce new post-CMOS technologies. The ideas are centred upon a novel network-centric multiprocessor architecture, with contributions planned at every level from the circuit to the language level.'