PERSEUS

3D modelling of the performance and variability of high electron mobility transistors for future digital applications

Coordinatore	SWANSEA UNIVERSITY    more  Organization address address: SINGLETON PARK city: SWANSEA postcode: SA2 8PP contact info Titolo: Dr. Nome: Karol Cognome: Kalna Email: send email Telefono: +44 1792 606678 Fax: +44 1792 295676
Nazionalità Coordinatore	United Kingdom [UK]
Totale costo	200˙371 €
EC contributo	200˙371 €
Programma	FP7-PEOPLE Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
Code Call	FP7-PEOPLE-2011-IEF
Funding Scheme	MC-IEF
Anno di inizio	2013
Periodo (anno-mese-giorno)	2013-02-01   -   2015-01-31

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	SWANSEA UNIVERSITY  Organization address address: SINGLETON PARK city: SWANSEA postcode: SA2 8PP contact info Titolo: Dr. Nome: Karol Cognome: Kalna Email: send email Telefono: +44 1792 606678 Fax: +44 1792 295676	UK (SWANSEA)	coordinator	200˙371.80

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 Obiettivo del progetto (Objective)

'The current bulk transistor technology will not deliver an ITRS prescribed on-current at and beyond the 22 nm technology generation. A radical change in the device architecture will occur to sustain the device performance and reduce power dissipation. For this reason, Intel has recently announced that they will use a non-planar, 3D Tri-Gate architecture in mass production for the 22 nm technology. In this highly interdisciplinary proposal, we will analyse the feasibility of two novel MOSFETs based on III-V materials channel as future contenders for digital applications. These transistors are Implant Free Quantum Well devices and III-V on insulator FinFETs. Their performance and scalability will be assessed for three technological nodes (22, 16 and 12 nm). We will also study the impact that different sources of intrinsic parameter fluctuations have on their performance and reliability. The effect of the random dopants, gate work-function, oxide or interface charge variability on the threshold voltage, subthreshold slope or on-current of the devices will be evaluated and the impact on circuit design determined. Hierarchical device simulation approaches will be employed, including 2D and 3D Non-Equilibrium Green´s Functions, 2D and 3D Finite-Element Monte Carlo, and 3D Finite-Element Drift-Diffusion simulations. The numerical algorithms implemented in these simulation tools will be optimised and parallelised in order to minimise the computational cost. We will analyse different resolution methods, like Krylov subspace solvers and multigrid techniques, assisted by preconditioners, including domain decomposition methods, which are employed in the solution of the linear systems of equations. The simulation codes will be ported to and optimised for different computational infrastructures, such as high performance computers, Grid and Cloud.'