FiPS
Developing Hardware and Design Methodologies for Heterogeneous Low Power Field Programmable Servers
| Coordinatore | OFFIS EV
Organization address
address: Escherweg 2 contact info |
| Nazionalità Coordinatore | Germany [DE] |
| Totale costo | 3˙922˙597 € |
| EC contributo | 3˙098˙463 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2013-10 |
| Funding Scheme | CP |
| Anno di inizio | 2013 |
| Periodo (anno-mese-giorno) | 2013-09-01 - 2016-08-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
OFFIS EV
Organization address
address: Escherweg 2 contact info |
DE (OLDENBURG) | coordinator | 0.00 |
| 2 |
CENTRE DE RECHERCHE EN AERONAUTIQUE ASBL - CENAERO
Organization address
city: GOSSELIES contact info |
BE (GOSSELIES) | participant | 0.00 |
| 3 |
CHRISTMANN INFORMATIONSTECHNIK + MEDIEN GMBH & CO KG
Organization address
address: ILSEDER HUTTE contact info |
DE (ILSEDE) | participant | 0.00 |
| 4 |
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Organization address
address: RUE LEBLANC contact info |
FR (PARIS 15) | participant | 0.00 |
| 5 |
COSYNTH GMBH & CO. KG
Organization address
address: ESCHERWEG contact info |
DE (OLDENBURG) | participant | 0.00 |
| 6 |
INSTYTUT CHEMII BIOORGANICZNEJ POLSKIEJ AKADEMII NAUK
Organization address
address: NOSKOWSKIEGO 12-14 contact info |
PL (POZNAN) | participant | 0.00 |
| 7 |
NATIONAL UNIVERSITY OF IRELAND, GALWAY
Organization address
address: University Road contact info |
IE (GALWAY) | participant | 0.00 |
| 8 |
SOFISTIK HELLAS AE
Organization address
address: ODOS 3 SEPTEMBRIOU contact info |
EL (ATHINA) | participant | 0.00 |
| 9 |
UNIVERSITAET BIELEFELD
Organization address
address: UNIVERSITAETSSTRASSE contact info |
DE (BIELEFELD) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
The goal of this project is to reduce the power performance ratio within data-centres by improving the usability and usefulness of FPGAs, embedded CPU (eCPU), GPUs and multi/manycore accelerators in high-performance and low-power heterogeneous computing servers. We target applications between traditional super computing tasks (where huge amount of man-power can be spent for manual algorithm optimization) and general purpose data-centre applications (which have to run as they are w/o any optimization for hardware acceleration).nThe consortium consists of partners from embedded systems and high-performance computing domains. We will combine our experiences in automatic software-to-hardware synthesis and hardware-software co-design from the embedded systems world with the hardware and application experience from the high-performance computing world.nThe project focus will be on a) setting up a flexible server hardware system, offering a user-constrainted amount of CPUs, eCPUs, FPGAs, GPUs and multi/manycore processors; b) setting up a software development environment, easing up computing resources co-programming adapted fromexisting tools and runtime management techniques from the embedded system domain and leveraging state-of-the-art middle-ware communication and execution frameworks from the HPC domain; and c) demonstrate the effectiveness of both hardware and software environments from FiPS outputs with real world applications at four HPC application partners.