GOSSAMER
Gigascale Oriented Solid State flAsh Memory for EuRope
| Coordinatore |
Organization address
address: Numonyx Italy Srl - Contrada Blocco Torrazze Zona Industria 2 contact info |
| Nazionalità Coordinatore | Non specificata |
| Totale costo | 208˙116 € |
| EC contributo | 0 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Anno di inizio | 2008 |
| Periodo (anno-mese-giorno) | 2008-01-01 - 2011-06-30 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
MICRON SEMICONDUCTOR ITALIA SRL
Organization address
address: Numonyx Italy Srl - Contrada Blocco Torrazze Zona Industria 2 contact info |
IT (Catania) | coordinator | 0.00 |
| 2 |
ACTIVE TECHNOLOGIES SRL
Organization address
address: VIA SARAGAT 1 contact info |
IT (FERRARA) | participant | 0.00 |
| 3 |
ALMA CONSULTING GROUP SAS
Organization address
address: Domaine des Bois d'Houlbec contact info |
FR (HOULBEC COCHEREL) | participant | 0.00 |
| 4 |
ASM BELGIUM NV
Organization address
address: KAPELDREEF contact info |
BE (HEVERLEE) | participant | 0.00 |
| 5 |
ASM EUROPE BV
Organization address
address: VERSTERKERSTRAAT contact info |
NL (ALMERE) | participant | 0.00 |
| 6 |
ASM MICROCHEMISTRY OY
Organization address
address: VAINO AUERIN KATU contact info |
FI (HELSINKI) | participant | 0.00 |
| 7 |
CONSIGLIO NAZIONALE DELLE RICERCHE
Organization address
address: PIAZZALE ALDO MORO contact info |
IT (ROMA) | participant | 0.00 |
| 8 |
CONSORZIO NAZIONALE INTERUNIVERSITARIO PER LA NANOELETTRONICA
Organization address
address: VIA TOFFANO contact info |
IT (BOLOGNA) | participant | 0.00 |
| 9 |
FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V
Organization address
address: Hansastrasse contact info |
DE (MUENCHEN) | participant | 0.00 |
| 10 |
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Organization address
address: Kapeldreef contact info |
BE (LEUVEN) | participant | 0.00 |
| 11 |
JORDAN VALLEY SEMICONDUCTORS LTD
Organization address
address: INDUSTRIAL ZONE contact info |
IL (MIGDAL HAEMEK) | participant | 0.00 |
| 12 |
NaMLab gGmbH
Organization address
address: Nothnitzer Strasse contact info |
DE (Dresden) | participant | 0.00 |
| 13 |
POLITECNICO DI MILANO
Organization address
address: PIAZZA LEONARDO DA VINCI contact info |
IT (MILANO) | participant | 0.00 |
| 14 |
TECHNISCHE UNIVERSITAET BRAUNSCHWEIG
Organization address
address: POCKELSSTRASSE contact info |
DE (BRAUNSCHWEIG) | participant | 0.00 |
| 15 |
UNIVERSITA DEGLI STUDI DI FERRARA
Organization address
address: SAVONAROLA contact info |
IT (FERRARA) | participant | 0.00 |
| 16 |
UNIVERSITA DEGLI STUDI DI MODENA E REGGIO EMILIA
Organization address
address: VIA UNIVERSITA contact info |
IT (MODENA) | participant | 0.00 |
| 17 |
UNIVERSITA DEGLI STUDI DI UDINE
Organization address
address: VIA PALLADIO contact info |
IT (UDINE) | participant | 0.00 |
| 18 |
UNIVERSITY COLLEGE CORK, NATIONAL UNIVERSITY OF IRELAND, CORK
Organization address
address: Western Road contact info |
IE (CORK) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
The project aims at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 2X nm technology node. The field is receiving increasing attention, due to the explosion of portable multimedia applications, and is forecasted to exceed 40 Billion US$ total available market by 2010. The dominant technology for this application is the floating gate NAND memory. However severe technological roadblocks (reduction in storage charge and electrostatic interference among neighboring cells) are limiting further scaling beyond the 32 nm node. Charge trapping in dielectric layers seems to be a viable alternative to floating gate. The main challenge is the integration of the different new materials, like tunnel dielectric, trapping layer, top dielectric, metal gate at the target technology node and the achievement of an acceptable trade-off between functionality and reliability (e.g. charge retention and endurance). The project will cover material development, cell architecture, modeling of material properties, trapping and conduction behavior in the dielectrics, metal gate materials. Initial studies could be performed on available technology 65-45nm (more relaxed for Universities and research centers) to arrive to full process integration and realization of full arrays in a technology in the 28-36 nm range (the best achievable with available lithography) by two major European semiconductor manufacturers. It will include memory characterization and reliability testing, with the additional aim of defining standards and procedures for reliability assessment. Technology options for higher integration densities, for a given lithography node, will be investigated with the help of public research partners. The final demonstrator will be a fully working memory array in the multi-gigabit range.